MTJ Top Electrode Layout for Via Punch-Through Protection
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Solution Overview
Problem
The semiconductor industry faces challenges in controlling the position of interconnect structures during fabrication, leading to issues such as via punch through, damage to memory cells, and leakage, particularly due to thermal budget constraints and the shrinking dimensions of memory cells.
Innovation Solution
A semiconductor device and fabrication method that utilize a 'top electrode-last' approach with a wider top electrode connecting multiple memory cells, along with a specific etch stop stack and protection layer configuration, to alleviate via punch through and thermal budget issues, ensuring compatibility with mature interconnection fabrication processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via formation methods are used, then interconnect structures can be formed, but via punch through and damage to memory cells occur due to position control issues
Solution Approach 1:
The patent introduces an etch stop layer positioned between the via structure and the memory cell to prevent direct contact and potential damage. This intermediary layer acts as a protective barrier that stops the etching process before it can penetrate into the memory cell region, thereby preventing via punch through while maintaining via position control
Solution Approach 2:
The etch stop layer is formed in advance before via etching occurs. This preliminary action ensures that the protective layer is already in place to prevent damage during subsequent etching operations, addressing the position control and damage prevention issues proactively
2Manufacturing precision
If etching duration is extended to ensure complete via formation, then via connectivity is improved, but thermal budget constraints are exceeded causing damage to memory cells
Solution Approach 1:
The etch stop layer serves as a visual and physical marker that indicates when the etching process has reached the appropriate depth. By monitoring etching progress relative to the etch stop layer position, the process can be stopped at the optimal point without exceeding thermal budget constraints
Solution Approach 2:
The etch stop layer provides feedback during the etching process about the current etching depth and progress. This allows real-time monitoring and adjustment of etching duration to ensure complete via formation without excessive thermal exposure that would damage memory cells
3Quantity of substance
If memory cell dimensions are reduced to increase density, then storage capacity is improved, but control of interconnect position becomes more difficult leading to leakage
Solution Approach 1:
The etch stop layer acts as a reference marker that becomes increasingly important as memory cell dimensions shrink. It provides a stable positional reference that helps maintain interconnect position control even when surrounding features are reduced in size
Solution Approach 2:
The patent changes the approach from direct dimensional control to reference-based control. By using the etch stop layer as a positional reference, the system can maintain manufacturing precision through parameter changes in the etching process rather than relying solely on absolute dimensional tolerances
4Reliability
If standard protection layers are used, then basic protection is provided, but they are incompatible with mature interconnection fabrication processes
Solution Approach 1:
The etch stop layer is designed with specific material properties and thickness parameters that are compatible with mature interconnection fabrication processes. By adjusting these parameters, the protection mechanism can be integrated into existing manufacturing workflows without requiring process overhauls
Solution Approach 2:
The protection function is segmented into a dedicated etch stop layer rather than relying on a single multifunctional protection layer. This segmentation allows the protection layer to be optimized for its specific function while maintaining compatibility with other fabrication processes
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a first metal line over a first region of the substrate, a first magnetic tunnel junction (MTJ) and a second MTJ over the first region of the substrate, and a top electrode extending over the first MTJ and the second MTJ, wherein the top electrode includes a protruding portion at a bottom surface of the top electrode.