MTJ Etch Stop Layer for Reliable Upper Interconnect Landing
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Solution Overview
Problem
The challenge of forming a reliable electrical connection between the top electrode and the interconnect wire in magnetic tunnel junction (MTJ) devices, such as MRAM, is exacerbated by the difficulty in landing the interconnect wire due to over-etching, which can damage the MTJ and reduce yield, especially as device sizes shrink.
Innovation Solution
Incorporating an etch stop layer over the MTJ device to protect it during fabrication, allowing for separate processes to expose and remove the etch stop layer, thereby forming an upper interconnect wire without significant damage to the MTJ, thus improving the process window and reducing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etch stop layer is added to protect the MTJ during fabrication, then the reliability and process window are improved, but the device complexity and fabrication steps increase
Solution Approach 1:
An etch stop layer is deposited over the MTJ structure before subsequent interconnect formation steps. This preliminary protective action ensures that the MTJ is safeguarded against damage during later etching processes, while the layer can be selectively removed afterward to expose the MTJ for electrical contact.
Solution Approach 2:
The etch stop layer serves as an intermediary protective element between the MTJ and the etching tools. It temporarily absorbs the mechanical and chemical stress of fabrication processes, allowing the delicate MTJ to remain intact throughout manufacturing.
2Manufacturing precision
If separate processes are used to expose and remove the etch stop layer, then the manufacturing precision is improved, but the productivity decreases
Solution Approach 1:
The fabrication process is segmented into distinct stages: etch stop layer deposition, interconnect formation with improved overlay accuracy, and selective etch stop layer removal. This segmentation allows each step to be optimized independently, with the etch stop layer providing a stable reference plane for precise patterning.
Solution Approach 2:
The etch stop layer is deposited in advance to establish a stable reference plane for subsequent photolithography and etching steps. This preliminary action improves overlay accuracy by providing a uniform surface, and the layer is removed only after it has served its protective and alignment functions.
Data Source
AI summary
The present disclosure relates to an integrated chip in some embodiments. The integrated chip includes an inter-level dielectric (ILD) laterally surrounding a memory device. One or more sidewall spacers are arranged along opposing sides of the memory device. The one or more sidewall spacers have a bottom surface over a bottom of the memory device. An etch stop layer is disposed on the one or more sidewall spacers and along the opposing sides of the memory device. An upper interconnect is arranged directly over the memory device, a top surface of the one or more sidewall spacers, and an upper surface of the etch stop layer. The upper surface of the etch stop layer is vertically below a top of the memory device.