MTJ with Hf/Ru Capping to Reduce Spin-Transfer Switching Current
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Solution Overview
Problem
Current Spin-RAM technologies face challenges in achieving a critical current density (Jc) less than 1.0×10^6 A/cm^2 and a high tunnel magnetoresistance ratio (TMR) of at least 120% with a low resistance-area (RA) value, while maintaining compatibility with CMOS transistors and avoiding electrical breakdown.
Innovation Solution
A Magnetic Tunneling Junction (MTJ) configuration is developed with a bottom spin valve structure, featuring a synthetic anti-ferromagnetic pinned layer, amorphous CoFeB free layer, and a Hf/Ru capping layer, which reduces the 'dead layer' at the free layer/capping interface, using a crystalline MgO tunnel barrier formed by radical oxidation, and annealing at 250-300°C to ensure amorphous CoFeB layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional MTJ configuration is used, then the device structure is simple, but the critical current density is too high (greater than 1.0×10^6 A/cm^2) and TMR ratio is insufficient
Solution Approach 1:
The patent employs composite material structures including synthetic anti-ferromagnetic pinned layers combining CoFe and CoFeB, amorphous CoFeB free layers, and Hf/Ru capping layer composites. These composite materials enable simultaneous achievement of low critical current density (less than 1.0×10^6 A/cm^2) and high TMR ratio (greater than 120%) while maintaining structural integrity and compatibility with CMOS fabrication processes.
Solution Approach 2:
The patent optimizes multiple parameters including the thickness of each layer (CoFe: 10-20 nm, CoFeB: 15-25 nm, MgO: 2-4 nm), annealing temperature (250-300°C), and composition ratios to achieve the desired balance between critical current density and TMR ratio. The synthetic anti-ferromagnetic structure with specific coupling field strengths and the amorphous phase of CoFeB layers are critical parameter choices that enable the performance targets.
2Reliability
If the TMR ratio is increased to improve memory signal, then the resistance-area (RA) value increases causing higher power consumption
Solution Approach 1:
The patent achieves high TMR ratio (greater than 120%) with low RA value through precise parameter optimization including MgO barrier thickness (2-4 nm), CoFeB layer thickness (15-25 nm), and annealing temperature (250-300°C). These parameter changes enable the tunnel magnetoresistance ratio to exceed 120% while maintaining RA values that result in acceptable power consumption for CMOS-compatible Spin-RAM devices.
3Ease of operation
If high current density is applied to switch magnetization, then magnetization switching is achieved, but electrical breakdown occurs in the tunnel barrier
Solution Approach 1:
The patent reduces the critical current density to less than 1.0×10^6 A/cm^2 through the synthetic anti-ferromagnetic pinned layer structure and amorphous CoFeB free layer, enabling magnetization switching at lower current densities that do not cause electrical breakdown in the MgO tunnel barrier. The annealing process at 250-300°C further enhances the dielectric breakdown voltage while maintaining the amorphous phase of CoFeB layers.
Solution Approach 2:
The patent employs a CMOS-compatible fabrication process that uses standard semiconductor manufacturing techniques and materials, making the technology economically viable and scalable. The process integrates seamlessly with existing CMOS fabrication lines, enabling mass production of Spin-RAM devices without requiring specialized or expensive equipment.
4Reliability
If amorphous CoFeB layers are maintained through low temperature annealing, then the dead layer is minimized, but crystalline structure is not achieved
Solution Approach 1:
The patent maintains the amorphous phase of CoFeB layers by controlling the annealing temperature between 250-300°C, which is sufficient to minimize the dead layer at the free layer/capping layer interface but below the crystallization temperature of CoFeB. This parameter control achieves the optimal balance between minimizing dead layer thickness and maintaining the amorphous structural stability of the CoFeB layers.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration achieves a Jc less than 1.0×10^6 A/cm^2, a TMR ratio greater than 120%, and a low RA value, suitable for spin-transfer magnetization switching, with improved thermal stability and dielectric breakdown voltage, enhancing the performance of Spin-RAM devices.
Implementation Method 1
a crystalline MgO tunnel barrier formed by radical oxidation
Implementation Method 2
The tunnel barrier layer is thin enough that a current through it can be established by quantum mechanical tunneling of conduction electrons
Implementation Method 3
annealing at 250-300°C to ensure amorphous CoFeB layers
Implementation Method 4
reduces spin transfer magnetization switching current
Data Source
AI summary
A MTJ that minimizes spin-transfer magnetization switching current (Jc) in a Spin-RAM to <1×106 A/cm2 is disclosed. The MTJ has a Co60Fe20B20/MgO/Co60Fe20B20 configuration where the CoFeB AP1 pinned and free layers are amorphous and the crystalline MgO tunnel barrier is formed by a ROX or NOX process. The capping layer preferably is a Hf/Ru composite where the lower Hf layer serves as an excellent oxygen getter material to reduce the magnetic “dead layer” at the free layer/capping layer interface and thereby increase dR/R, and lower He and Jc. The annealing temperature is lowered to about 280° C. to give a smoother CoFeB/MgO interface and a smaller offset field than with a 350° C. annealing. In a second embodiment, the AP1 layer has a CoFeB/CoFe configuration wherein the lower CoFeB layer is amorphous and the upper CoFe layer is crystalline to further improve dR/R and lower RA to ≦10 ohm/μm2.