MTJ LUT Finalization for Secure FPGA Configuration Bits
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Solution Overview
Problem
Existing non-volatile flash-based FPGAs face reliability issues due to environmental and malicious stimuli, and volatile SRAM-based FPGAs have limited switching times, necessitating a solution that combines the flexibility of multiple-time programmable (MTP) and one-time programmable (OTP) capabilities while ensuring security and reliability.
Innovation Solution
The integration of magneto-tunnel junction (MTJ)-based field programmable gate arrays (FPGAs) with selective conversion to OTP capabilities, utilizing MTJ-based cells that allow for increased write endurance and switching times, and the addition of permanent configuration bit programming to secure configuration bits against tampering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If MTP capability is provided using MTJ-based cells, then flexibility and reprogrammability are improved, but security and reliability against environmental and malicious stimuli deteriorate
Solution Approach 1:
The configuration memory is divided into multiple banks, each containing MTJ-based configuration cells. This segmentation allows selective programming and finalization of different configuration regions, enabling the system to maintain MTP capabilities in unfinalized banks while ensuring security in finalized banks, thus resolving the contradiction between reprogrammability and security
Solution Approach 2:
The system dynamically transitions from MTP mode to OTP mode through a finalization process. Initially, all configuration cells are in MTP state allowing reprogramming. When security requirements are met, the system selectively finalizes configuration cells, transitioning them to OTP state where they can no longer be reprogrammed. This dynamic state transition enables the system to adapt its programmability characteristics based on security needs
2Reliability
If permanent configuration bit programming is added to convert MTP to OTP, then security and reliability are improved, but device complexity increases
Solution Approach 1:
The finalization circuitry is integrated within the existing FPGA architecture, merging the OTP conversion functionality with the MTP configuration system. The same MTJ cells and control logic that enable MTP operation are extended to provide finalization capability, rather than adding completely separate OTP hardware, thus minimizing the increase in device complexity while achieving enhanced security
Solution Approach 2:
The configuration memory system serves multiple functions: it provides MTP capability for initial programming and updates, OTP capability for finalized secure configurations, and the ability to transition between these states. The same hardware infrastructure supports both MTP and OTP operation modes, reducing overall system complexity compared to maintaining separate MTP and OTP systems
3Duration of action of moving object
If MTJ-based cells are used, then write endurance is improved, but switching times increase compared to SRAM-based FPGAs
Solution Approach 1:
The system applies different operational characteristics to different configuration scenarios. For frequent reconfigurations during development and testing, the system leverages the non-volatile nature of MTJ cells which maintain configuration without power. For production deployments, the system performs finalization to OTP state, eliminating the need for repeated switching. This local optimization of switching behavior based on operational context mitigates the impact of slower MTJ switching times
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the reliability and security of FPGA configurations by providing increased write endurance and switching times, while ensuring resistance to environmental and malicious stimuli, effectively transitioning from MTP to OTP capabilities for secure and flexible programming.
Implementation Method 1
MTJ-based cells allow increased write endurance performance compared to existing non-volatile flash-based FPGAs. MTJ-based cells also offer increased switching times compared to volatile SRAM-based FPGAs.
Data Source
AI summary
Various embodiments include providing a MTJ-based LUT and adding a system that short circuits or causes dielectric layer breakdown of selected MTJ junctions to permanently finalize a desired logic state configuration of selected MTJs that is read out by the LUT. Additional embodiments disable dielectric layer breakdown or short circuit control circuits to prevent further alterations to MTJ that have not had their dielectric layers broken down or shorted out. A control system then alters reading out the MTJ-based LUT to sense original higher and lower resistance values of un-shorted/altered MTJs as a higher resistance state and a shorted or dielectric layer that has been broken down as a lower resistance state. This combines the flexibility of a multiple-time programmable LUT-based FPGA with the security and reliability of a one-time programmable LUT-based FPGA which has characteristics of a fixed logic non-programmable integrated circuit or application specific integrated circuit (ASIC).