MTJ Memory Cell Using Cross-Coupled N-Type Transistors
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Solution Overview
Problem
Current memory devices face challenges in achieving both high storage density and power efficiency, particularly in non-volatile memory cells, due to the larger size and leakage current of P-type transistors, which hinder area and power efficiency.
Innovation Solution
The implementation of a memory cell design that omits P-type transistors and uses cross-coupled N-type transistors with magnetic tunnel junction (MTJ) devices in different layers, allowing for area-efficient and power-efficient non-volatile memory operation by storing bits without power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If P-type transistors are used in non-volatile memory cells, then data storage capability is achieved, but area efficiency deteriorates due to larger transistor size
Solution Approach 1:
The patent extracts and removes P-type transistors from the memory cell structure, retaining only N-type transistors. This extraction eliminates the area overhead associated with P-type transistors while maintaining the essential data storage functionality through the remaining N-type transistor and MTJ device configuration.
Solution Approach 2:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where MTJ devices are positioned vertically above the N-type transistor gates. This dimensional change allows multiple memory cells to be stacked in the vertical direction, dramatically increasing storage density without proportionally increasing the footprint area.
2Quantity of substance
If P-type transistors are used in non-volatile memory cells, then data storage capability is achieved, but power efficiency deteriorates due to leakage current
Solution Approach 1:
The patent extracts and removes P-type transistors from the memory cell structure, retaining only N-type transistors. This extraction eliminates the area overhead associated with P-type transistors while maintaining the essential data storage functionality through the remaining N-type transistor and MTJ device configuration.
Solution Approach 2:
The patent changes the electrical parameters of the memory cell by replacing P-type transistors with N-type transistors, which have different threshold voltage characteristics and lower leakage current. This parameter change fundamentally alters the power consumption profile of the memory cell while maintaining functionality.
3Loss of energy
If cross-coupled N-type transistors with MTJ devices are used, then power efficiency is improved, but device complexity increases due to multi-layer structure
Solution Approach 1:
The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture where MTJ devices are positioned vertically above the N-type transistor gates. This dimensional change allows multiple memory cells to be stacked in the vertical direction, dramatically increasing storage density without proportionally increasing the footprint area.
Solution Approach 2:
The patent implements a nested structure where MTJ devices are positioned directly above the N-type transistor gates, with the MTJ tunnel barrier layer containing the storage node. This nesting allows the memory storage function to be integrated within the same footprint as the transistor, reducing overall device complexity despite the multi-layer construction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved storage density and power efficiency by eliminating the need for larger P-type transistors and reducing leakage current, enabling the memory cell to function as a non-volatile memory cell with efficient data storage and retrieval.
Implementation Method 1
a first magnetic tunnel junction (MTJ) device electrically coupled between a common node and the first node. In one aspect, the second MTJ device is disposed above another part of the cross-coupled transistors.
Implementation Method 2
The MTJ devices can store bits or data without power
Data Source
AI summary
Disclosed herein are related to a memory cell including magnetic tunneling junction (MTJ) devices. In one aspect, the memory cell includes a first layer including a first transistor and a second transistor. In one aspect, the first transistor and the second transistor are connected to each other in a cross-coupled configuration. A first drain structure of the first transistor may be electrically coupled to a first gate structure of the second transistor, and a second drain structure of the second transistor may be electrically coupled to a second gate structure of the first transistor. In one aspect, the memory cell includes a second layer including a first MTJ device electrically coupled to the first drain structure of the first transistor and a second MTJ device electrically coupled to the second drain structure of the second transistor. In one aspect, the second layer is above the first layer.