MTJ Memory Flatness via Ion Implantation Amorphization
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Solution Overview
Problem
Existing memory devices face challenges in securing the flatness of layers in Magnetic Tunnel Junction (MTJ) structures, which affects the characteristics of variable resistance elements used in memory cells, leading to deteriorated performance.
Innovation Solution
The implementation of an ion implantation process to amorphize the upper portion of the conductive pattern and interlayer dielectric layer, ensuring a flat top surface and incorporating dopants like Ge, Ar, Xe, In, Sb, or As, to form a semiconductor memory device with an MTJ structure that includes a free layer with a variable magnetization direction and a pinned layer with a pinned magnetization direction, thereby improving the flatness and performance of the variable resistance element.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for MTJ structures, then the manufacturing process is simpler, but the flatness of MTJ layers deteriorates leading to poor variable resistance element characteristics
Solution Approach 1:
An ion implantation process is performed before forming the MTJ structure to amorphize the upper portion of the conductive pattern and interlayer dielectric layer. This preliminary action creates a flat surface that prevents subsequent layer bending, ensuring good flatness of MTJ layers without requiring complex post-processing steps.
Solution Approach 2:
The physical state of the conductive pattern and interlayer dielectric layer is changed from crystalline to amorphous through ion implantation. This parameter change in the material structure enables the formation of a flat surface that maintains layer flatness during subsequent MTJ fabrication processes.
2Manufacturing precision
If ion implantation process is used to amorphize conductive pattern, then the flatness of MTJ structure is improved, but the manufacturing process becomes more complex
Solution Approach 1:
The ion implantation process is performed as a preliminary step before MTJ structure formation to amorphize the conductive pattern surface. This creates a flat foundation that simplifies subsequent MTJ layer deposition and ensures good flatness without requiring additional complex processing steps later.
Solution Approach 2:
Ion implantation changes the physical state of the conductive pattern from crystalline to amorphous, which fundamentally alters the material properties to achieve surface flatness. This parameter change enables the conductive pattern to maintain a flat surface during subsequent processing.
3Reliability
If the conductive pattern has a non-flat surface, then the fabrication process is simpler, but the variable resistance element characteristics deteriorate
Solution Approach 1:
Ion implantation is performed in advance to amorphize the conductive pattern and create a flat surface before MTJ structure formation. This preliminary action ensures that the variable resistance element characteristics are maintained by preventing layer bending, without requiring complex post-processing.
Solution Approach 2:
The physical state change from crystalline to amorphous through ion implantation enables the conductive pattern to provide a flat surface that maintains the reliability of variable resistance element characteristics during subsequent MTJ layer deposition.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach secures the flatness of the MTJ structure layers, preventing deterioration of the variable resistance element's characteristics and enhancing the data storage capabilities of the memory device, while simplifying the fabrication process.
Implementation Method 1
The implementation of an ion implantation process to amorphize the upper portion of the conductive pattern and interlayer dielectric layer
Implementation Method 2
amorphize the upper portion of the conductive pattern and interlayer dielectric layer, ensuring a flat top surface
Implementation Method 3
an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer
Implementation Method 4
incorporating dopants like Ge, Ar, Xe, In, Sb, or As, to form a semiconductor memory device
Data Source
AI summary
This technology provides an electronic device and a method for fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a hole; a conductive pattern filled in the hole and having a top surface located at a level substantially same as a top surface of the interlayer dielectric layer; and an MTJ (Magnetic Tunnel Junction) structure formed over the conductive pattern to be coupled to the conductive pattern and including a free layer having a variable magnetization direction, a pinned layer having a pinned magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, wherein an upper portion of the conductive pattern includes a first amorphous region.