Complementary MTJ Memory Sensing for Single Flip-Error Detection
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Solution Overview
Problem
Complementary Magnetic Tunneling Junction (MTJ) based memory bit-cells suffer from retention errors due to uncertain read issues when one MTJ flips, leading to conflicting sensing modes and increased reading latency, as existing solutions require complicated reading logic and 'Salvage Mode' to identify conflicts, which doubles read latency and power consumption.
Innovation Solution
A dual sense amplifier architecture is introduced, where a second sense amplifier detects errors simultaneously with the first, using an errors-and-erasures decoding process to improve error correction, eliminating the need for dual reading of complementary bit-cells and reducing read latency and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a second read mode (Salvage Mode) is employed to identify conflicts by reading the two MTJs separately, then retention error detection capability is improved, but reading latency increases
Solution Approach 1:
The patent combines the error detection function with the normal read operation by using a dual sense amplifier architecture. The first sense amplifier performs normal differential reading while the second sense amplifier simultaneously detects retention errors by reading both MTJs in the complementary bit-cell. This merging of functions eliminates the need for a separate Salvage Mode, thereby maintaining improved reliability while avoiding increased reading latency.
Solution Approach 2:
The patent implements preliminary error detection during the normal read operation itself. By having the second sense amplifier detect retention errors simultaneously with the first sense amplifier performing the normal read, the system performs error detection as a preliminary action rather than requiring a subsequent separate read operation. This approach maintains fast read latency while ensuring reliability.
2Reliability
If a second read mode (Salvage Mode) is employed to identify conflicts, then retention error detection capability is improved, but power consumption increases
Solution Approach 1:
The patent merges the error detection function with the normal read operation using a dual sense amplifier architecture. Both the first sense amplifier (for normal reading) and the second sense amplifier (for error detection) operate simultaneously during a single read cycle. This eliminates the need for a separate power-consuming Salvage Mode operation, thereby improving reliability while controlling power consumption.
3Reliability
If complicated reading logic is used to identify conflicts in complementary MTJ bit-cells, then retention error detection is improved, but device complexity increases
Solution Approach 1:
The patent segments the sensing function into two independent sense amplifiers: the first sense amplifier handles normal differential reading, while the second sense amplifier is dedicated to detecting retention errors. This segmentation allows each amplifier to perform its specific function with simple, dedicated logic rather than requiring a single complex reading logic unit to handle both normal reading and error detection.
Solution Approach 2:
The patent combines error detection capability with the normal read operation through the dual sense amplifier architecture. By integrating both functions into parallel amplifier circuits rather than using sequential complex logic control, the system achieves improved retention error detection while maintaining relatively simple device structure.
Data Source
AI summary
Described is an apparatus which comprises: a complementary resistive memory bit-cell; a first sense amplifier coupled to the complementary resistive memory bit-cell via access devices; a second sense amplifier coupled to the first sense amplifier and to the complementary resistive memory bit-cell via the access devices, wherein the second sense amplifier is operable to detect an error in the complementary resistive memory bit-cell.