MTJ Memory Cell Layout With Self-Aligned Bottom Electrode Via
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Solution Overview
Problem
The overlay alignment of patterned masks in magnetoresistive memory formations is challenging, and existing manufacturing processes are costly due to complex patterning requirements for magnetic tunnel junctions (MTJs) in integrated circuits.
Innovation Solution
A method involving the formation of a bottom via opening and a trench in a dielectric layer over a wafer, where a bottom electrode via is formed, and a bottom electrode layer is conformally deposited over it, along with a memory layer and a top electrode, which improves overlay alignment and reduces manufacturing costs by eliminating unnecessary process steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If complex patterning processes are used for MTJ formation, then manufacturing precision can be improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent employs self-aligned patterning where the bottom electrode via automatically serves as the alignment reference for subsequent layer deposition. The conformal deposition process uses the via structure itself to define the pattern, eliminating the need for separate alignment marks and complex photolithography steps. This self-service approach achieves high overlay precision while simplifying the manufacturing process.
Solution Approach 2:
The bottom electrode via is formed first with precise positioning, establishing the alignment reference before subsequent layers are deposited. This preliminary action ensures that all subsequent MTJ layers will be automatically aligned to the correct position, resolving the overlay alignment challenge without requiring complex real-time alignment processes.
2Manufacturing precision
If additional process steps are added to improve alignment, then manufacturing precision improves, but productivity decreases
Solution Approach 1:
The patent merges the alignment reference formation with the bottom electrode via creation process. Instead of adding separate alignment mark formation steps, the via structure itself serves dual purposes: as the electrical connection element and as the alignment reference. This consolidation maintains high alignment precision while improving productivity by reducing the total number of process steps.
3Manufacturing precision
If conformal deposition is used for bottom electrode layer, then manufacturing precision improves, but use of energy increases
Solution Approach 1:
The conformal deposition process applies material locally and uniformly only where needed - specifically on the sidewalls and bottom of the bottom electrode via. This localized conformal deposition achieves precise thickness control and uniform coverage without the energy waste associated with depositing material across entire wafer surfaces, as the deposition is confined to the specific via regions requiring the bottom electrode layer.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances signal transmission and alignment precision, allowing for more efficient patterning of memory cells and reducing manufacturing costs by simplifying the process without compromising conductivity or layer thickness.
Implementation Method 1
A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench
Data Source
AI summary
A method for manufacturing a memory device includes forming a dielectric layer over a wafer, wherein the wafer has a device region and a peripheral region adjacent to the device region. A bottom via opening is formed in the dielectric layer and over the device region of the wafer and a trench is formed in the dielectric layer and over the peripheral region of the wafer. A bottom electrode via is formed in the bottom via opening. A bottom electrode layer is conformally formed over the bottom electrode via and lining a sidewall and a bottom of the trench. A memory layer and a top electrode are formed over the bottom electrode layer.