Magnetic Tunnel Junction Memory With Stacked Conductive Patterns
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Solution Overview
Problem
Existing semiconductor devices face challenges in maintaining data integrity when power is interrupted, as non-volatile memory elements like FLASH memory devices are not as fast as magnetic memory devices, which are needed for integrated memory and logic functions on a single chip.
Innovation Solution
A semiconductor device design featuring a substrate with vertically spaced lower conductive patterns, a magnetic tunnel junction on the uppermost pattern, and an upper conductive line with increased thickness and width, along with interconnection lines, to form a memory element that can store data reliably and efficiently, using a magnetic tunnel junction with pinned and free layers to control resistance states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If non-volatile memory devices like FLASH memory are used to prevent data loss when power is interrupted, then data storage reliability is improved, but operation speed deteriorates compared to magnetic memory devices
Solution Approach 1:
The patent segments the memory system into multiple conductive patterns stacked vertically, with magnetic tunnel junctions positioned on specific patterns. This segmentation allows the device to achieve both non-volatile storage reliability and fast operation by utilizing the high-speed characteristics of magnetic memory while maintaining data retention through the magnetic tunnel junction structure
Solution Approach 2:
The patent employs composite material structures including magnetic tunnel junctions with pinned layers and free layers, combined with multiple conductive patterns and interconnection lines. This composite structure integrates the advantages of magnetic memory (fast operation) with non-volatile storage capabilities, resolving the contradiction between speed and reliability
2Reliability
If the upper conductive line has larger thickness and width than the lower conductive pattern, then current carrying capacity and signal integrity are improved, but manufacturing complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar conductive patterns to three-dimensional vertically stacked conductive patterns. By stacking multiple conductive patterns at different heights, the design achieves improved current carrying capacity and signal integrity without significantly increasing manufacturing complexity, as the vertical stacking can be implemented using standard semiconductor fabrication processes
Solution Approach 2:
The patent applies different dimensions and properties to different parts of the conductive structure. The upper conductive line has larger thickness and width locally where it is needed for current carrying, while the lower conductive patterns maintain smaller dimensions. This local quality variation optimizes signal integrity in critical areas without uniformly increasing device complexity
3Quantity of substance
If vertically spaced lower conductive patterns are stacked to form the memory structure, then integration density is improved, but fabrication precision requirements increase
Solution Approach 1:
The patent increases integration density by utilizing the vertical dimension through stacked conductive patterns. Multiple patterns are arranged at different heights rather than spreading them out in the plane, which achieves higher density while the vertical spacing between patterns provides tolerance for fabrication variations, reducing the impact of precision requirements
4Speed
If magnetic tunnel junctions with pinned and free layers are used to control resistance states, then data storage speed is improved, but device structure complexity increases
Solution Approach 1:
The magnetic tunnel junction is segmented into distinct functional layers including pinned layers and free layers, each performing a specific function. This segmentation allows for optimized performance and controllable resistance states while the modular layer structure can be fabricated using standard sequential deposition processes, managing complexity through functional decomposition
Solution Approach 2:
The patent uses composite material structures for the magnetic tunnel junction, combining different magnetic and non-magnetic layers with specific properties. This composite structure achieves fast data storage speed through controlled magnetization states while the layered composite design follows conventional magnetic memory fabrication techniques, keeping structure complexity manageable
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances data storage reliability by using magnetic tunnel junctions to control resistance states, allowing for faster operation and minimizing process changes in logic structure formation, thus preventing fabrication failures and ensuring high reliability with a simple process.
Implementation Method 1
a magnetic tunnel junction provided on an uppermost lower conductive pattern of the plurality of lower conductive patterns
Implementation Method 2
using a magnetic tunnel junction with pinned and free layers to control resistance states
Data Source
AI summary
A first lower interconnection structure and a second lower interconnection structure are formed using a first design rule on a first region of a substrate and a second region of the substrate, respectively. A memory element is formed on the first lower interconnection structure. The memory element includes a bottom electrode, a magnetic tunnel junction and a top electrode stacked on each other. An upper conductive line and an upper interconnection line are formed using a second design rule larger than the first design rule on the first lower interconnection structure and the second lower interconnection structure, respectively. The first lower interconnection structure, the memory element and the upper conductive line are stacked on each other so that the memory element is interposed between the first lower interconnection structure and the upper conductive line.