MTJ Memory Wiring With Direct Vias to Reduce Parasitic Capacitance
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Solution Overview
Problem
Spin transfer torque-magnetic random access memory (STT-MRAM) faces challenges in integration density and electrical issues due to high integration requirements and parasitic capacitance, particularly with the limitations of metal wire connections in semiconductor processes.
Innovation Solution
The proposed memory design omits the third metal wire connection between wiring layers by using via holes to directly connect metal wires, reducing parasitic capacitance and allowing for more efficient circuit wiring, thereby improving integration density and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional metal wire connections between wiring layers are used, then electrical connectivity is achieved, but parasitic capacitance increases and integration density decreases
Solution Approach 1:
The patent extracts and removes the intermediate third metal wire connection from the conventional wiring structure. By eliminating this redundant conductive layer and its associated interfaces, the design reduces parasitic capacitance while maintaining electrical connectivity through direct via-hole connections between the first and second metal wires.
Solution Approach 2:
The patent transitions from a planar two-dimensional wiring arrangement to a three-dimensional vertical stacking configuration. Multiple wiring layers are stacked vertically with via holes providing direct inter-layer connections, eliminating the need for intermediate horizontal metal wire connections and reducing parasitic capacitance in the process.
2Reliability
If conventional metal wire connections between wiring layers are used, then electrical connectivity is achieved, but integration density decreases
Solution Approach 1:
The patent extracts and removes the intermediate third metal wire connection from the conventional wiring structure. By eliminating this redundant conductive layer and its associated interfaces, the design reduces parasitic capacitance while maintaining electrical connectivity through direct via-hole connections between the first and second metal wires.
Solution Approach 2:
The patent transitions from a planar two-dimensional wiring arrangement to a three-dimensional vertical stacking configuration. Multiple wiring layers are stacked vertically with via holes providing direct inter-layer connections, eliminating the need for intermediate horizontal metal wire connections and reducing parasitic capacitance in the process.
3Object-generated harmful factors
If via holes directly connect metal wires across wiring layers, then parasitic capacitance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates the via hole formation and metal wire connection processes into the preliminary stages of the semiconductor manufacturing sequence. By integrating these steps into the existing fabrication flow before final assembly, the design achieves reduced parasitic capacitance without significantly increasing overall manufacturing complexity.
Data Source
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Figure 3~4
Figure 5(a)~5(b)
AI summary
This application provides a memory, and relates to the field of semiconductor technologies, to improve integration density of the memory. A memory, where each storage unit in a storage area includes a transistor and an MTJ storage element; a bottom electrode of the MTJ storage element is electrically connected to a drain electrode of the transistor by using a conduction structure; a plurality of wiring layers are disposed between the transistor and the MTJ storage element in the storage area, and a dielectric layer is filled between adjacent wiring layers; the conduction structure includes a first conduction part, and the first conduction part includes a first metal wire, a second metal wire, and a first via hole; the plurality of wiring layers comprise a first wiring layer, a second wiring layer, and a third wiring layer; the first via hole penetrates a dielectric layer and the third wiring layer that are located between the first wiring layer and the second wiring layer; and a first connection passage is disposed in the first via hole, the first connection passage is directly connected to the first metal wire at the first wiring layer and the second metal wire at the second wiring layer, and the first connection passage is not directly connected to a metal wire at the third wiring layer.