MTJ Structure Integration for MRAM Scalability
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Solution Overview
Problem
Conventional MRAM cell structures are susceptible to short circuits and sidewall damage as they scale down, leading to failures, and existing techniques to mitigate these issues are limited by logic technology and inefficient.
Innovation Solution
The MTJ fabrication process is modified to reduce bottom electrode contact resistance, improve gap filling performance, and minimize sidewall damage through the use of a planarized layer with a contact layer embedded in the bottom electrode, and a partial MTJ etch to enhance size and shape control, along with chemical mechanical polishing to reduce surface roughness.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MRAM cell structures are used, then fabrication is simpler, but short circuits and sidewall damage increase as device size scales down
Solution Approach 1:
The patent segments the bottom electrode formation process into distinct stages: first forming a planarized layer over the substrate, then embedding the contact layer within the bottom electrode structure. This segmentation allows each layer to be optimized independently - the planarized layer provides a flat surface for precise MTJ patterning while the embedded contact layer ensures low contact resistance without causing short circuits between adjacent cells.
Solution Approach 2:
The patent introduces a vertical dimension solution by stacking multiple layers (planarized layer, bottom electrode, contact layer, MTJ stack) in the thickness direction. This vertical integration resolves the horizontal scaling problem by moving functionality to different elevation levels, allowing continued device miniaturization in the plane while maintaining reliable electrical connections through the layered structure.
2Quantity of substance
If MTJ size continues to scale down, then memory density increases, but sidewall damage and patterning challenges increase
Solution Approach 1:
The patent performs preliminary planarization by forming the planarized layer before depositing the MTJ stack. This pre-planarization ensures that the surface is sufficiently flat before subsequent lithography and etching steps, enabling precise patterning of smaller MTJ devices without sidewall damage. The planarized layer acts as a sacrificial element that protects the underlying structure during processing.
Solution Approach 2:
The patent changes the physical and chemical parameters of the planarized layer to optimize its protective function. By controlling the thickness, material composition, and surface properties of the planarized layer, the patent creates an ideal substrate that enables high-precision patterning of scaled-down MTJ structures while preventing sidewall damage during fabrication.
3Manufacturing precision
If bottom electrode contact resistance is high, then MTJ gap filling performance is poor, but reducing contact resistance may increase short circuit risk
Solution Approach 1:
The patent introduces the contact layer as an intermediary element between the bottom electrode and the MTJ stack. This intermediate layer serves dual functions: it provides low contact resistance for excellent electrical connection and gap filling performance, while simultaneously acting as a protective barrier that prevents direct contact between adjacent bottom electrodes, thereby eliminating short circuit risks.
Solution Approach 2:
The patent replaces the conventional direct-contact bottom electrode structure with a multi-layer composite structure. Instead of relying on a single thick bottom electrode layer, the patent uses a sophisticated stack of planarized layer, bottom electrode, and contact layer, where each layer contributes specific electrical and mechanical properties to achieve both low contact resistance and short circuit prevention.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the occurrence of short circuits, improves MTJ size and shape control, and enhances the scalability of MRAM cells, enabling lower-cost, higher-density memory chip fabrication while maintaining compatibility with logic back-end-of-line integration.
Implementation Method 1
chemical mechanical polishing to reduce surface roughness
Implementation Method 2
Due to the tunneling magnetoresistance effect, the electrical resistance of the cell changes due to the relative moment orientation of the polarizations in the two magnetic layers of the MTJ
Implementation Method 3
spin-transfer-torque (STT) MRAM uses spin-aligned or polarized electrons to directly torque and flip the magnetic moment of the free layer
Data Source
AI summary
A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.