Non-volatile Memory Cell with MTJ Elements for Power Reduction
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Solution Overview
Problem
Conventional SRAM-based cache memories consume high standby and operating power due to leakage currents, and replacing them with non-volatile SRAMs can reduce standby power but not operating power, while existing non-volatile SRAMs with six transistors and magnetic tunnel junctions face challenges in reducing operating power consumption.
Innovation Solution
A non-volatile memory cell configuration using four transistors and two magnetic tunnel junction (MTJ) elements, where the MTJ elements are strategically placed between transistors and wiring lines to eliminate leakage current paths, allowing for bi-directional current flow for writing non-volatile data and independent data storage without shared wiring lines, reducing power consumption and preventing data loss.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SRAM-based cache memory is used, then high-speed SRAM operations are achieved, but standby power consumption increases due to leakage currents
Solution Approach 1:
The patent merges SRAM and non-volatile memory (NVM) into a single hybrid memory cell structure. The six-transistor SRAM cell is integrated with two magnetic tunnel junction (MTJ) elements, creating a unified cell that provides both volatile SRAM functionality and non-volatile data retention capabilities, thereby reducing standby power while maintaining operation speed
Solution Approach 2:
The patent uses composite memory structure combining different memory technologies - volatile SRAM transistors and non-volatile MTJ magnetic elements. This composite approach leverages the high-speed characteristics of SRAM and the non-volatile properties of MTJ to achieve both fast operation and low standby power consumption
2Use of energy by stationary object
If non-volatile SRAM with six transistors and two MTJ elements is used, then standby power consumption is reduced, but operating power consumption cannot be reduced due to leakage current paths
Solution Approach 1:
The patent extracts and eliminates the leakage current path from the hybrid memory cell structure. By carefully designing the transistor connections and MTJ placements, the patent removes the continuous leakage path that exists in conventional six-transistor non-volatile SRAM, thereby reducing both standby and operating power consumption simultaneously
3Loss of energy
If MTJ elements are placed between transistors and wiring lines, then leakage current paths are eliminated and independent data storage is achieved, but device complexity increases
Solution Approach 1:
The patent segments the memory cell into distinct functional regions - volatile storage nodes, non-volatile MTJ elements, and isolated bit lines. This segmentation allows independent data storage in each region and eliminates unwanted current paths between them, achieving low leakage while maintaining manageable complexity through modular design
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration effectively reduces both standby and operating power consumption while preventing SRAM data loss by eliminating leakage current paths and allowing independent data storage, enhancing the reliability and efficiency of non-volatile memory operations.
Implementation Method 1
two magnetic tunnel Junction (MTJ) elements as magnetoresistive memory devices
Implementation Method 2
non-volatile characteristics
Data Source
AI summary
A non-volatile memory of an embodiment includes a plurality of memory cells, each of the memory cells including a plurality of transistors including a first to fourth transistors, a first non-volatile element, a second non-volatile element, a first node, and a second node, the first and second transistors being connected in series with the first non-volatile element, the third and fourth transistors being connected in series with the second non-volatile element, the first node being disposed between the first and second transistors, the second node being disposed between the third and fourth transistors, gates of the first and third transistors being connected to one of first wiring lines, a gate of the second transistor being connected to the second node, a gate of the fourth transistor being connected to the first node, the first transistor being connected between one of second wiring lines and the first node.