MTJ Pattern Layout for MRAM CMP Planarization
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Solution Overview
Problem
The challenge in MRAM devices is to minimize delamination of dielectric layers between word lines and bit lines during CMP processing while achieving superior planarization, as reduced MTJ sizes lead to increased device failure and delamination issues, and existing methods struggle with controlling the distance between interconnects and MTJ elements effectively.
Innovation Solution
A novel MTJ pattern layout is introduced, featuring dummy MTJ devices and dual dummy bands around active MTJ device blocks, which includes a substructure with metal layers and insulating layers, allowing for improved CMP planarization by preventing delamination and reducing dishing and protrusions, and the use of a specific etch and deposition sequence to form these elements and bands.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If MTJ size is reduced to satisfy higher performance requirements, then device density and speed are improved, but delamination of dielectric layers during CMP processing increases
Solution Approach 1:
The patent applies preliminary action by forming a planarization layer of dielectric material over the interconnect structure before completing the bit line formation. This preliminary planarization prevents delamination during subsequent CMP processing by providing a protective dielectric layer that maintains structural integrity, allowing reduced MTJ sizes for higher density without compromising reliability
2Productivity
If distance between bit line and MTJ free layer is reduced to maximize writing efficiency, then write operation performance is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent uses an intermediary approach by introducing a planarization layer of dielectric material between the bit line and the MTJ structure. This intermediary layer allows precise control of the distance between the bit line and MTJ free layer, enabling optimized writing efficiency while maintaining manufacturability through standard deposition and planarization processes
3Manufacturing precision
If CMP processing is used to planarize dielectric layers, then surface flatness is improved, but delamination of dielectric layers occurs
Solution Approach 1:
The patent applies beforehand cushioning by depositing an additional layer of dielectric material (planarization layer) over the interconnect structure before CMP processing. This cushioning layer absorbs the mechanical stress during CMP, preventing delamination of the underlying dielectric layers while still achieving the required surface flatness for subsequent processing
Data Source
AI summary
An MTJ pattern layout for a memory device is disclosed that includes two CMP assist features outside active MTJ device blocks. A first plurality of dummy MTJ devices is located in two dummy bands formed around an active MTJ device block. The inner dummy band is separated from the outer dummy band by the MTJ ILD layer and has a MTJ device density essentially the same as the MTJ device block. The outer dummy band has a MTJ device density at least 10% greater than the inner dummy band. The inner dummy band serves to minimize CMP edge effect in the MTJ device block while the outer dummy band improves planarization. A second plurality of dummy MTJ devices is employed in contact pads outside the outer dummy band and is formed between a WL ILD layer and a BIT ILD layer thereby minimizing delamination of the MTJ ILD layer.