MTJ PUF Cell Array for Low-Power Secure Challenge Responses
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Solution Overview
Problem
The increasing need for secure access to sensitive information in electronic devices is challenged by manufacturing variations and misalignment tolerances in semiconductor fabrication, which existing PUF technologies struggle to address effectively, particularly in terms of immunity to machine learning attacks and efficient power consumption.
Innovation Solution
A physically unclonable function (PUF) generator using a PUF cell array with one transistor and two MTJ memory cells, where bit cells store data based on resistance states, allowing for challenge-response pairs that provide higher immunity to machine learning attacks and improved power efficiency by reducing the number of components and read current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional PUF technologies are used, then device uniqueness is achieved, but immunity to machine learning attacks deteriorates
Solution Approach 1:
The PUF cell is segmented into two distinct MTJ memory cells (first and second MTJ cells) with different resistance states, allowing the system to generate unique responses based on the combination of these segmented components. This segmentation enables higher immunity to machine learning attacks by creating more complex physical variations that are harder to model.
Solution Approach 2:
Different regions of the PUF cell are assigned different properties: the first MTJ cell has a first resistance state while the second MTJ cell has a second resistance state. This local quality differentiation creates unique physical characteristics at each location, enhancing security against machine learning attacks while maintaining a relatively simple overall cell structure.
2Reliability
If more components are used in PUF cells, then security is improved, but power consumption increases
Solution Approach 1:
Multiple functions are merged into a single PUF cell structure: data storage, unique identification, and security credential generation are all achieved within one cell containing two MTJ memory cells. This merging reduces the need for additional components that would increase power consumption, while still providing high security through the combined functionality.
Solution Approach 2:
The PUF cell with two MTJ memory cells serves multiple purposes: it stores data bits, generates unique device identifiers, and provides security credentials for authentication. This multi-functionality eliminates the need for separate components for each function, thereby reducing overall power consumption while maintaining high security standards.
3Manufacturing precision
If manufacturing precision is improved, then device uniformity is enhanced, but physical uniqueness deteriorates
Solution Approach 1:
The patent converts the harmful effect of manufacturing variations and misalignment tolerances into a beneficial feature. By designing the PUF cell to rely on inherent differences between the first and second MTJ cells (which arise from normal manufacturing variations), the system transforms imprecision into the source of physical uniqueness needed for security applications.
Solution Approach 2:
The invention changes the approach from seeking uniformity in physical parameters to utilizing variations in resistance states of the two MTJ cells. By measuring and comparing the resistance parameters of the first and second MTJ cells, the system generates unique identifiers based on natural manufacturing variations rather than requiring precise control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances area utilization, power consumption, and operation speed, providing a unique identity for integrated circuits while improving resistance to machine learning attacks and reducing energy consumption.
Implementation Method 1
Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.
Implementation Method 2
a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line
Implementation Method 3
a transistor having a control terminal coupled to a word line
Data Source
AI summary
A device is provided. The device includes a physical unclonable function (PUF) cell array. The PUF cell array includes multiple bit cells, and generates a PUF response output, in response to a challenge input, based on a data state of one bit cell in the bit cells. Each of the bit cells stores a bit data and includes a transistor having a control terminal coupled to a word line and a first terminal coupled to a source line, a first memory cell having a first terminal coupled to a first data line and a second terminal coupled to a second terminal of the transistor, and a second memory cell having a first terminal coupled to a second data line, different from the first data line, and a second terminal coupled to the second terminal of the first memory cell at the second terminal of the transistor.