Magnetic Tunnel Junction Register Cell for Low Power Nonvolatile Logic
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Solution Overview
Problem
Conventional logic ICs and FPGAs face challenges with high power consumption due to leakage currents and the need for external nonvolatile memory, which limits their scalability, density, and reprogramming speed, while existing nonvolatile SRAM technologies are costly and have low endurance.
Innovation Solution
A register cell and shift register design incorporating magnetic tunnel junctions, which form an unbalanced flip-flop circuit with PMOS and NMOS transistors, allowing for low power consumption and nonvolatile data storage through thermally assisted switching and external magnetic field manipulation, enabling high-density integration and fast reprogramming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional volatile logic ICs are used, then fast operation speed is achieved, but power consumption increases due to leakage current and external nonvolatile memory is required
Solution Approach 1:
The patent combines volatile logic circuit functionality with nonvolatile memory functionality into a single integrated cell structure. The magnetic tunnel junction (MTJ) is integrated directly into the logic cell, merging the roles of volatile storage (flip-flop) and nonvolatile storage (MTJ) into one unified device, eliminating the need for separate external nonvolatile memory while maintaining fast operation speeds.
Solution Approach 2:
The magnetic tunnel junction acts as an intermediary element that bridges the volatile logic circuit and nonvolatile storage requirements. The MTJ provides nonvolatile data retention while the logic circuit operates at full speed, with the MTJ serving as the mediating interface between these two functional requirements.
2Reliability
If external nonvolatile memory is integrated, then nonvolatile data storage is achieved, but access time increases and reprogramming speed decreases
Solution Approach 1:
By merging the nonvolatile MTJ storage element directly into the logic cell, the patent eliminates the time delay associated with accessing external nonvolatile memory. The MTJ is positioned within the same cell as the logic circuit, enabling immediate data retention and fast reprogramming without the access time penalties of external memory integration.
3Reliability
If flash memory is used for nonvolatile storage, then data retention is achieved, but additional masks and process steps are required increasing chip cost
Solution Approach 1:
The patent merges the MTJ nonvolatile storage element with the logic cell fabrication process, allowing both to be manufactured together in the same CMOS process. This integration eliminates the need for separate flash memory fabrication steps, additional masks, and dedicated process steps, thereby reducing chip cost while maintaining data retention capabilities.
4Reliability
If nonvolatile SRAM technology is used, then nonvolatile storage is achieved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the nonvolatile storage function from complex nonvolatile SRAM architectures and implements it using a simpler magnetic tunnel junction element. By taking out the essential nonvolatile storage capability and implementing it through the MTJ within a standard logic cell, the design achieves nonvolatile storage without the excessive device complexity and cost associated with nonvolatile SRAM technologies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The magnetic tunnel junction-based design reduces power consumption, eliminates the need for external nonvolatile memory, and provides high-timing performance, reliable data storage, and low additional mask requirements, enhancing the flexibility and efficiency of logic ICs.
Implementation Method 1
non volatile logic devices using magnetic tunnel junctions
Implementation Method 2
heating the selected magnetic tunnel junctions
Implementation Method 3
external magnetic field manipulation
Data Source
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AI summary
The present disclosures concerns a register cell (1) comprising a differential amplifying portion (2) containing a first inverter (3) coupled to a second inverter (3') such as to form an unbalanced flip-flop circuit; a first and second bit line (BL0, BL1) connected to one end of the first and second inverter (3, 3'), respectively; and a first and second source line (SL0, SL1) connected to the other end of the first and second inverter (3, 3'), respectively; characterized by the register cell (1) further comprising a first and second magnetic tunnel junction (6, 6') electrically connected to the other end of the first and second inverter (3, 3'), respectively. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low. The shift register disclosed herein can be made smaller than conventional shift registers and power consumption during the write and read operation of the shift registers can be low.