Retention Flip-Flop Using MTJ Resistive Memory for Power Gating
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Solution Overview
Problem
Current methods for power gating in processors, such as using Always-ON memory units or flip-flops, incur significant power consumption and area overhead, and suffer from high write energy, slow entry/exit from sleep modes, and retention failure probabilities due to the need for separate power supplies and leakage currents.
Innovation Solution
The use of resistive memory elements, specifically MTJ devices, in a retention flip-flop design that eliminates the need for Always-ON power supplies by storing data magnetically, allowing for efficient save and restore operations with improved write and restore margins, and reduced power consumption by using existing core supply voltages down to 0.7V, and configuring MTJ devices in series paths to prevent read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Always-ON memory units are used for data retention during power gating, then data retention is achieved, but power consumption and area overhead increase significantly
Solution Approach 1:
The patent extracts the retention function from the main logic block by using a separate retention flip-flop that can operate independently. The retention flip-flop is isolated from the main power domain, allowing the main logic to be fully powered down while a minimal retention circuit maintains data. This separation eliminates the need for large Always-ON memory units, reducing both power consumption and area overhead while maintaining data retention capability.
2Productivity
If state retention flip-flops with Always-ON supply are used, then fast save and restore is achieved, but leakage power consumption increases and area overhead remains
Solution Approach 1:
The patent implements periodic action by using clock-gated transparency in the retention flip-flop. The flip-flop is transparent only during specific clock periods when data needs to be saved or restored, and opaque during other periods to minimize leakage. This allows fast save and restore operations when needed while significantly reducing continuous leakage power consumption compared to Always-ON supply configurations.
3Reliability
If data is moved to Always-ON memory arrays for retention, then data is preserved, but save and restore operations take time and incur power penalty
Solution Approach 1:
The patent segments the flip-flop structure into a retention portion and a main logic portion. The retention flip-flop is a simplified version that keeps only the essential data storage and clocking functionality, removing unnecessary circuitry. This segmentation allows the retention circuit to be much smaller and faster than full memory arrays, enabling rapid data preservation and restoration without the time penalties associated with large memory structures.
4Reliability
If separate Always-ON power supply is routed to each retention flip-flop, then data retention is enabled, but device complexity and area overhead increase
Solution Approach 1:
The patent makes the retention flip-flop universal by designing it to share the same power supply domain as the main logic when active, eliminating the need for separate Always-ON power routing. The retention circuit can be selectively powered using the existing power infrastructure through clock and control signals, making it multi-functional and compatible with standard power distribution networks. This reduces device complexity and removes the burden of routing dedicated Always-ON supplies to each retention element.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption during sleep modes, enhances write and restore operations, and increases reliability by eliminating leakage power and area overhead, while maintaining compatibility with existing designs and improving margins against variations.
Implementation Method 1
an MTJ device including: a free magnetic layer coupled to the first p-type device and the first n-type device; and a fixed magnetic layer coupled to the second p-type device and the second n-type device
Implementation Method 2
The use of resistive memory elements, specifically MTJ devices, in a retention flip-flop design that eliminates the need for Always-ON power supplies by storing data magnetically
Data Source
AI summary
Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.