MTJ Embedding in Semiconductor Structure for N16 Nodes
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Solution Overview
Problem
As CMOS technology nodes shrink, the thickness of inter-metal dielectric (IMD) in the back-end-of-line (BEOL) scales down, making it challenging to accommodate the magnetic tunneling junction (MTJ) stack within the conventional embedding scheme, especially at technology nodes N16 and beyond, where the IMD thickness becomes too thin to properly fit the MTJ stack.
Innovation Solution
The integration of an MTJ between an Nth metal line and an (N+M)th metal via, where N is an integer greater than or equal to 1, and M is an integer greater than or equal to 1, allowing for lateral correspondence with metal line and via structures in the logic region, such as between the 3rd metal line and 4th metal via, to accommodate the MTJ stack thickness of approximately 1000 to 1200 Å.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If CMOS technology nodes are shrunk to improve device scaling and integration density, then productivity and integration density are improved, but the thickness of inter-metal dielectric (IMD) is reduced making it impossible to accommodate MTJ stack
Solution Approach 1:
The patent transitions from vertical embedding (between adjacent metal lines in the same layer) to lateral embedding (between metal lines of different layers, specifically between an Nth metal line and an (N+M)th metal via). This dimensional change allows the MTJ stack to span multiple metal layers, effectively utilizing the third dimension (vertical spacing between layers) to accommodate the MTJ thickness requirement while maintaining scaling in the planar dimensions.
Solution Approach 2:
The MTJ stack is nested between the Nth metal line and the (N+M)th metal via, which themselves are nested within the multi-layer interconnect structure. The MTJ stack thickness of 1000-1200 Å is accommodated by the vertical spacing created by the nested metal layers, allowing the MTJ to be embedded within the existing interconnect hierarchy without requiring additional lateral space.
2Reliability
If MTJ stack thickness is maintained at 1000 to 1200 Å to ensure device functionality, then reliability is improved, but the device cannot be embedded in reduced IMD thickness at technology nodes N16 and beyond
Solution Approach 1:
By embedding the MTJ stack laterally between metal lines of different layers rather than vertically between adjacent metal lines in the same layer, the patent utilizes the vertical dimension (spacing between metal layers) to accommodate the fixed MTJ thickness requirement. This allows the MTJ stack to maintain its required 1000-1200 Å thickness while fitting within the scaled-down IMD structure at technology nodes N16 and beyond.
Solution Approach 2:
The patent changes the spatial parameters of the embedding structure by introducing a layer offset M between the Nth metal line and the (N+M)th metal via. This parameter change allows the vertical distance between the embedding boundaries to be increased, providing sufficient space for the MTJ stack to maintain its required thickness while accommodating the reduced overall IMD thickness at advanced technology nodes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the embedding of MRAM cells with MTJs in CMOS technology nodes N16 and beyond by adjusting the metal layer and via structures, ensuring the MTJ stack fits within the reduced IMD thickness, maintaining device functionality and performance.
Implementation Method 1
The magnetization direction of free layer can be reversed by applying a current through tunnel layer, which causes the injected polarized electrons within free layer to exert so-called spin torques on the magnetization of free layer.
Implementation Method 2
The electrons are polarized to the same magnetization direction of pinned layer after passing pinned layer
Implementation Method 3
The electrons having the same polarization as the magnetization direction of pinned layer are able to flow through tunnel layer and into pinned layer.
Data Source
AI summary
The present disclosure provides a semiconductor structure, including a logic region and a memory region adjacent to the logic region. The memory region includes a first Nth metal line of an Nth metal layer, a magnetic tunneling junction (MTJ) over first Nth metal line, and a first (N+1)th metal via of an (N+1)th metal layer, the first (N+1)th metal via being disposed over the MTJ layer. N is an integer greater than or equal to 1. A method of manufacturing the semiconductor structure is also disclosed.