Magnetic Tunnel Junction Spacer Structure for DMI and TMR Control

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Solution Overview

Problem

Magnetic memory devices require high integration density and improved reliability to meet the demands of fast operating speed and low power consumption, which existing magnetic tunnel junction structures struggle to achieve effectively.

Innovation Solution

A magnetic tunnel junction structure with a first and second spacer layer of the same material, where the thickness of the first spacer layer ranges from 1 nm to 3.5 nm, is used in a spin-orbit-torque magnetic memory device, enabling enhanced Dzyaloshinskii-Moriya interaction and tunnel magnetoresistance properties for improved performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the magnetic tunnel junction structure uses conventional spacer layer configurations, then the device structure is simpler, but the integration density and reliability are insufficient

Engineering Contradiction:
ImprovereliabilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The magnetic tunnel junction structure is segmented into multiple functional layers including a first spacer layer (1-3.5 nm), first magnetic layer, second spacer layer, and second magnetic layer. This segmentation allows each layer to perform specific functions (spin-orbit interaction, magnetization control, DMI enhancement) thereby improving reliability through optimized layer-by-layer design

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different spacer layers are designed with specific thickness ranges (first spacer: 1-3.5 nm, second spacer: 1-3 nm) and positioned at different locations within the MTJ structure. The first spacer layer near the metal layer optimizes spin-orbit torque, while the second spacer layer enhances DMI, creating local quality variations that improve overall device reliability

Inventive Principle:
Principle #3Local quality

2Reliability

If the spacer layer thickness is not optimized, then the manufacturing process is simpler, but the DMI and TMR properties are insufficient

Engineering Contradiction:
ImproveDMI and TMR propertiesVSAvoidspacer layer thickness control
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

The spacer layer thickness is optimized to specific parameter ranges (first spacer: 1-3.5 nm, second spacer: 1-3 nm) to maximize Dzyaloshinskii-Moriya interaction and tunnel magnetoresistance effects. These parameter changes enable strong spin-orbit coupling and controlled magnetization switching while maintaining manufacturability through standard thin-film deposition techniques

Inventive Principle:
Principle #35Parameter changes

3Speed

If the magnetic memory device uses existing MTJ structures, then the device complexity is lower, but the operating speed and power consumption performance are insufficient

Engineering Contradiction:
Improveoperating speedVSAvoidMTJ structure complexity
Core Design Contradiction:
SpeedVSDevice complexity

Solution Approach 1:

The magnetic tunnel junction structure employs asymmetric layer configuration where the first spacer layer (1-3.5 nm) and second spacer layer (1-3 nm) have different thickness ranges, and the metal layer is positioned specifically adjacent to the first spacer layer. This asymmetry optimizes spin-orbit torque for fast magnetization switching while enabling low-power operation through enhanced spin Hall effect

Inventive Principle:
Principle #4Asymmetry

Solution Approach 2:

The first spacer layer acts as an intermediary between the metal layer and the first magnetic layer, facilitating spin-orbit interaction and enabling efficient spin current injection. This intermediary structure allows fast magnetization switching without requiring high current densities, thereby improving operating speed and reducing power consumption

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration allows for a magnetic memory device with high integration density and improved reliability, enabling fast operation speed and low power consumption by controlling the magnetization direction of the free layer and maintaining DMI and TMR properties.

Implementation Method 1

A magnetic tunnel junction structure with a first and second spacer layer of the same material, where the thickness of the first spacer layer ranges from 1 nm to 3.5 nm, is used in a spin-orbit-torque magnetic memory device, enabling enhanced Dzyaloshinskii-Moriya interaction and tunnel magnetoresistance properties

Methodology Applied
Scientific EffectDzyaloshinskii-Moriya interaction:

Implementation Method 2

The magnetic tunnel junction structure may include a first spacer layer, a first magnetic layer on the first spacer layer, and a second spacer layer on the first magnetic layer... the resistance of the magnetic tunnel junction structure may be high when the magnetization directions of the magnetic layers are antiparallel to each other and may be low when the magnetization directions of the magnetic layers are parallel to each other

Methodology Applied
Scientific EffectTunnel magnetoresistance: Magnetoresistance

Data Source

PatentUS20230301199A1Magnetic tunnel junction structure and magnetic memory device including the same
Publication Date: 2023.09.21 SAMSUNG ELECTRONICS CO LTD
  • US20230301199A1 patent drawing
  • US20230301199A1 patent drawing
  • US20230301199A1 patent drawing

AI summary

Disclosed are a magnetic tunnel junction structure and a magnetic memory device including the same. The magnetic tunnel junction structure may include a first spacer layer, a first magnetic layer on the first spacer layer, and a second spacer layer on the first magnetic layer. The first spacer layer and the second spacer layer may include a same material, and a thickness of the first spacer layer may range from 1 nm to 3.5 nm.