MTJ Sidewall Oxidation and Spacer Etch for MRAM Data Retention
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Solution Overview
Problem
Conventional reactive ion etch (RIE) and ion beam etch (IBE) processes used in forming magnetic tunnel junction (MTJ) cells cause electrical shorting and chemical/physical damage to sidewalls, leading to reduced magnetoresistive ratio and pinning strength, especially as cell size decreases below 60 nm, affecting data retention and fabrication costs.
Innovation Solution
A method involving an MTJ stack with an oxidized outer portion of the free layer and a dielectric spacer adjoining a capping layer, where the free layer's center portion is ferromagnetic and has a width less than the pinned layer and tunnel barrier widths, preventing sidewall damage and electrical shorting, and enhancing pinning strength and data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional RIE or IBE etching processes are used to form MTJ cells, then pattern transfer is achieved, but electrical shorting and chemical/physical damage to sidewalls occur
Solution Approach 1:
A dielectric spacer layer is introduced as an intermediary protective barrier between the etching environment and the MTJ sidewalls. The spacer is deposited conformally over the MTJ stack and patterned to extend beyond the MTJ footprint, physically isolating the sidewalls from direct exposure to etching chemicals and ions during RIE or IBE processes, thereby preventing both chemical damage and physical sputtering while allowing pattern transfer to proceed
Solution Approach 2:
The dielectric spacer is deposited and patterned in advance before the actual MTJ etching process. This preliminary protective structure is formed with dimensions that ensure complete coverage of the MTJ sidewalls during subsequent etching steps, preventing damage before it can occur rather than attempting to repair it afterward
2Productivity
If cell size is reduced to increase device density, then more cells per area are achieved, but sidewall damage becomes more severe
Solution Approach 1:
The dimensions of the dielectric spacer are specifically optimized as a function of MTJ cell size. As cell dimensions shrink, the spacer width and height are adjusted to maintain adequate protective coverage, ensuring that even at 60nm and below, the spacer sufficiently extends beyond the MTJ footprint to protect sidewalls from etching damage while not excessively increasing the overall cell footprint
3Reliability
If additional trimming steps are added to remove sidewall damage, then sidewall quality is improved, but fabrication cost and cycle time increase
Solution Approach 1:
Instead of adding more etching steps to remove damage, the approach converts the potential harm of etching into a beneficial protective process. The dielectric spacer transforms the etching environment from harmful to useful, as the same RIE or IBE equipment and processes that would normally damage the sidewalls are used to form the protective spacer structure itself, eliminating the need for additional trimming steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents electrical shorting and chemical damage to MTJ sidewalls, maintaining magnetic properties and improving data retention by ensuring the pinned layer has greater pinning strength on the free layer, even at smaller cell sizes, while reducing fabrication costs and cycle time.
Implementation Method 1
a free layer having an oxidized outer portion and a ferromagnetic center portion
Implementation Method 2
a dielectric spacer adjoins a capping layer such that the dielectric spacer and interface are coplanar, and electrical shorting is avoided
Implementation Method 3
enhancing pinning strength and data retention... the pinned layer has greater pinning strength on the free layer
Data Source
AI summary
A magnetic tunnel junction (MTJ) that avoids electrical shorts and has improved data retention is disclosed. An uppermost capping layer has a first sidewall that is coplanar with an interface between outer oxidized portions and a center ferromagnetic portion of a free layer (FL) that has a FL width (FLW). A dielectric spacer is formed on the first sidewall and oxidized outer FL portions. The pinned layer (PL) has a width (PLW) substantially greater than FLW, and a second sidewall thereon is formed by a self-aligned etch using the dielectric spacer and capping layer as an etch mask. A sidewall layer may be formed on the second sidewall and dielectric spacer but does not degrade MTJ properties since the sidewall layer does not contact the FL and PL center portions responsible for device performance. PL width>FLW ensures greater capability for data retention especially for FLW<60 nm.