MTJ Stack Composite Texture Breaking Layer TMR Enhancement
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Solution Overview
Problem
Current magnetic memory devices face challenges in achieving an enhanced tunneling magnetoresistance (TMR) ratio, which is crucial for next-generation magnetic memory cells, while also requiring a solution that addresses high temperature concerns and is cost-effective and compatible with logic processing.
Innovation Solution
The method involves forming a magnetic tunnel junction (MTJ) stack with a composite texture breaking layer that includes a ruthenium layer and a synthetic antiferromagnetic (SAF) layer, along with a polarizer layer, to enhance TMR and thermal budget, ensuring compatibility with CMOS BEOL processing and reducing diffusivity issues at high annealing temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional MTJ structure is used, then the device structure is simple, but the TMR ratio is insufficient for next-generation magnetic memory cells
Solution Approach 1:
The patent employs composite materials by introducing a texture breaking layer composed of multiple layers including Ru, CoFeB, and Ta. This composite structure enhances the TMR ratio by modifying the magnetic and structural properties of the MTJ, specifically by breaking the coherent spin scattering and improving spin polarization, thereby resolving the contradiction between maintaining structural simplicity and achieving high TMR ratio.
Solution Approach 2:
The texture breaking layer is segmented into multiple sub-layers (Ru layer, CoFeB layer, Ta layer) with distinct functions. The Ru layer provides spin scattering, the CoFeB layer contributes to magnetic properties, and the Ta layer offers structural stability. This segmentation allows each layer to optimize its contribution to TMR enhancement while maintaining overall structural manageability.
2Manufacturing precision
If high annealing temperatures are applied to enhance TMR, then the TMR performance improves, but thermal budget concerns and reliability issues arise
Solution Approach 1:
The patent modifies the structural parameters of the MTJ by introducing the texture breaking layer with specific thicknesses and material compositions. This structural parameter change enables the system to achieve high TMR performance at lower annealing temperatures, thereby improving thermal budget compatibility and reliability without sacrificing TMR enhancement.
3Adaptability or versatility
If process compatibility with logic processing is prioritized, then CMOS BEOL compatibility is achieved, but cost-effectiveness and process optimization are challenged
Solution Approach 1:
The texture breaking layer structure serves multiple functions: it enhances TMR ratio, improves thermal stability, ensures CMOS BEOL compatibility, and maintains compatibility with existing fabrication processes. This multi-functionality allows the patent to achieve process compatibility without significantly increasing manufacturing complexity or cost, as the same structural modification addresses multiple performance requirements simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in sustainable and enhanced TMR performance at high annealing temperatures, improving thermal budget and compatibility with CMOS BEOL processes, thereby enabling reliable and efficient magnetic memory devices.
Implementation Method 1
The resistance state of the MTJ element changes corresponding to that of the magnetic orientation of the free layer relating to the fixed layer, which may be in either a parallel (P) state or an anti-parallel (AP) state. The corresponding electrical resistance between the free layer and the fixed layer in P state is denoted as RP while the corresponding electrical resistance between the free layer and the fixed layer in AP state is denoted as RAP.
Implementation Method 2
The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a ruthenium layer and a synthetic antiferromagnetic (SAF) layer.
Data Source
AI summary
A device and a method of forming a device are presented. A substrate is provided. The substrate includes circuit component formed on a substrate surface. Back end of line processing is performed to form an upper inter level dielectric (ILD) layer over the substrate. The upper ILD layer includes a plurality of ILD levels. A magnetic tunneling junction (MTJ) stack is formed in between adjacent ILD levels of the upper ILD layer. The MTJ stack comprises a free layer, a tunneling barrier layer and a fixed layer. The fixed layer includes a polarizer layer, a composite texture breaking layer which includes a ruthenium layer and a synthetic antiferromagnetic (SAF) layer.