MTJ Stack Memory Integration for Non-Volatile SRAM
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Solution Overview
Problem
Integrating SRAM and flash memory into a single circuit or chip is challenging due to their different manufacturing processes and complexity, and even when integrated, it may consume extra area on the integrated circuit, while SRAM loses data when power is off and flash memory has slower write speeds compared to SRAM.
Innovation Solution
A semiconductor integrated circuit is developed with a manufacturing method that includes forming shallow trench isolation regions, dielectric layers, conductive vias, and magnetic tunnel junction (MTJ) layers, allowing for the integration of SRAM and flash memory-like functionality in a single chip with improved write current efficiency, where MTJ stacks of different sizes function as both SRAM and flash memory depending on write pulse speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If SRAM is used for rapid data access, then read and write speed is improved, but data is lost when power is turned off
Solution Approach 1:
The patent combines SRAM and flash memory into a single integrated circuit, allowing the system to leverage both the high-speed access of SRAM and the non-volatile data retention of flash memory within the same device structure
Solution Approach 2:
The integrated memory circuit performs multiple functions by incorporating both volatile SRAM functionality for rapid access and non-volatile flash memory functionality for data persistence, enabling a single device to handle both speed-critical and retention-critical operations
2Reliability
If flash memory is used for data retention without power, then data is preserved during power loss, but write speed becomes slower
Solution Approach 1:
The patent integrates flash memory with SRAM in a unified circuit architecture, enabling the system to use SRAM for rapid write operations when power is available and flash memory for data retention when power is lost, thereby improving overall write speed while maintaining data persistence
3Area of stationary object
If SRAM and flash memory are integrated into a single chip, then space consumption is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent merges SRAM and flash memory fabrication processes into a single integrated manufacturing flow, sharing common process steps such as trench isolation, dielectric layer formation, and conductive via creation, thereby reducing overall manufacturing complexity despite the functional integration
Solution Approach 2:
The integrated memory circuit uses universal manufacturing processes that serve both SRAM and flash memory formation, with certain process steps being common to both memory types, thereby simplifying the overall fabrication procedure while achieving dual-functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a single chip to retain data without power loss and achieve rapid write speeds, balancing the advantages of SRAM and flash memory while minimizing space consumption, effectively addressing the integration and performance issues of existing memory technologies.
Implementation Method 1
a magnetic tunnel junction (MTJ) layer, the patterned MTJ stack layer having a first MTJ stack of a first size and a second MTJ stack of a second size
Data Source
AI summary
The present disclosure relates to a semiconductor integrated circuit which includes a substrate, a first patterned conductive layer, a first magnetic tunnel junction (MTJ) stack and a second MTJ stack. The first patterned conductive layer is over the substrate. The first MTJ stack, which is over the first patterned conductive layer, has a first size. The second MTJ stack, which is over the first patterned conductive layer, has a second size different from the first size.