MTJ Memory Structure With Stop Layer for Via Short Prevention
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Solution Overview
Problem
As CMOS technology nodes scale down, the thickness of inter-metal dielectric (IMD) in the back-end-of-line (BEOL) becomes significantly thinner, leading to a processing barrier that prevents the reduction of the magnetic tunneling junction (MTJ) stack thickness, resulting in a reduced room for accommodating upper metal layers, which can cause short circuits between the upper metal and the MTJ.
Innovation Solution
A semiconductor structure is developed with a top electrode cap and a first stop layer over the MTJ in the memory region to prevent short circuits, along with a first (N+1)th metal via surrounded by the stop layer, and a second stop layer over the (N+1)th metal line in the logic region, where the first height of the (N+1)th metal via is greater than the second height, allowing for effective prevention of short circuits and accommodating upper metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the thickness of inter-metal dielectric (IMD) is reduced to accommodate scaling down, then the room for accommodating upper metal layers is reduced, but this leads to short circuits between the upper metal and the MTJ
Solution Approach 1:
The patent introduces an additional vertical dimension by adding a cap layer over the top electrode and adjusting via heights, creating a multi-level vertical structure that resolves the horizontal space constraint caused by thinning IMD layers
Solution Approach 2:
The cap layer acts as an intermediary protective element between the top electrode and the upper metal via, preventing direct contact and potential short circuits while allowing the via to maintain its electrical connection function
2Ease of operation
If the MTJ stack thickness is reduced, then the room for accommodating upper metal layers is reduced, but this causes short circuits between the upper metal and the MTJ
Solution Approach 1:
The solution moves the protection mechanism to the vertical dimension by implementing a cap layer and differentiated via heights, allowing thin MTJ stacks while maintaining reliable isolation from upper metal layers
Solution Approach 2:
The cap layer is selectively applied only over the MTJ structure in the memory region, providing localized protection where it is most needed while allowing other regions to maintain their original design characteristics
3Manufacturing precision
If the (N+1)th metal via is positioned over the MTJ, then the via height must be precisely controlled, but this creates shifting issues and reduces process window
Solution Approach 1:
The cap layer serves as a cushioning element that absorbs positioning variations and provides a more forgiving target for via formation, reducing the impact of alignment errors and expanding the acceptable process window
Solution Approach 2:
The cap layer acts as an intermediary reference plane that simplifies the via formation process by providing a distinct, easily identifiable target that is less sensitive to underlying structure variations
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents short circuits between the upper metal and the MTJ, maintaining the integrity of the MTJ stack and ensuring reliable operation by creating a wider process window for the (N+1)th metal via landing and preventing shifting issues, thus addressing the challenge of scaling down while maintaining structural integrity.
Implementation Method 1
A semiconductor structure is developed with a top electrode cap and a first stop layer over the MTJ in the memory region to prevent short circuits
Data Source
AI summary
The present disclosure provides a semiconductor structure. The semiconductor structure includes a memory region, the memory region includes a first metal line, a magnetic tunneling junction (MTJ) over the first metal line, a cap, wherein at least a portion of the cap is above the MTJ, a first stop layer above the cap, and a first metal via being disposed over the MTJ and in direct contact with the first stop layer, and a logic region adjacent to the memory region, the logic region includes a second metal line, a third metal line over the second metal line, a second stop layer being disposed over the third metal line, and a second metal via over the third metal line.