MTJ Memory Device Stress Inducing Layers for Sidewall Profile Control
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Solution Overview
Problem
Existing semiconductor memory devices with variable resistance elements, such as Magnetic Tunnel Junctions, face challenges in maintaining optimal magnetic and electrical characteristics due to oblique sidewall profiles and prolonged etch processes, which lead to deteriorated performance and increased risk of redeposition of etch byproducts.
Innovation Solution
The implementation of a semiconductor memory device with a variable resistance element that includes a Magnetic Tunnel Junction structure, where a first protective layer applies compressive stress to the free layer and a second protective layer applies tensile stress to the pinned layer, using a two-step etch process to achieve a substantially vertical profile, thereby improving magnetic characteristics and preventing volume deformation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a conventional etch process is used to form the variable resistance element, then the etch process can be completed, but the sidewall profile becomes oblique and magnetic characteristics deteriorate
Solution Approach 1:
The etch process is divided into two separate steps: a first etch process to form an initial structure, and a second etch process to complete the variable resistance element. This segmentation allows for better control of the sidewall profile and prevents oblique formation, thereby maintaining optimal magnetic characteristics.
Solution Approach 2:
A first protective layer is formed on the sidewall before the etch processes to protect against oblique profile formation. This preliminary protective action ensures that the sidewall maintains a vertical profile throughout the etching, preventing deterioration of magnetic characteristics.
2Productivity
If etch time is prolonged to ensure complete etching, then the etch process is thorough, but redeposition of etch byproducts increases and performance deteriorates
Solution Approach 1:
The etch process is segmented into two steps with different durations and purposes. The first etch process removes the initial layer, and the second etch process completes the etching. This segmentation reduces the total etch time required while ensuring complete removal of material, thereby minimizing redeposition of etch byproducts.
Solution Approach 2:
The patent rushes through the etching process by using two quick etch steps instead of one prolonged etch step. This approach minimizes the time during which etch byproducts can redeposit, thereby maintaining device performance.
3Reliability
If stress is not applied to the variable resistance element, then the structure remains simple, but magnetic and electrical characteristics are suboptimal
Solution Approach 1:
Different protective layers are applied to different regions of the variable resistance element: a first protective layer on the lower sidewall and a second protective layer on the upper sidewall. Each layer has different stress characteristics (compressive or tensile), allowing local optimization of magnetic and electrical characteristics without requiring complex global restructuring.
Solution Approach 2:
The patent changes the stress parameter by introducing protective layers with different stress types (compressive and tensile). This parameter change optimizes the magnetic and electrical characteristics of the variable resistance element. The first protective layer applies compressive stress while the second applies tensile stress, creating optimal conditions for device performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the magnetic and electrical characteristics of the variable resistance element by controlling stress application and reducing etch time, minimizing the redeposition of etch byproducts and maintaining optimal performance.
Implementation Method 1
a first protective layer applies compressive stress to the free layer
Implementation Method 2
a second protective layer applies tensile stress to the pinned layer
Data Source
AI summary
An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a variable magnetization direction, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer; a first protective layer disposed on a lower sidewall of the variable resistance element; and a second protective layer disposed on an upper sidewall of the variable resistance element, wherein any one layer of the first protective layer and the second protective layer may apply a compressive stress to the variable resistance element, and the other layer applies a tensile stress to the variable resistance element.