MTP Flash Memory Cell Array Program Disturb Reduction
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Solution Overview
Problem
Current multiple-time programmable (MTP) flash memory cell arrays experience program disturb issues, affecting the endurance performance of memory devices due to voltage differences during programming operations.
Innovation Solution
The proposed solution involves a novel MTP flash memory cell array configuration with specific voltage application conditions, including varying voltages for bit lines, word lines, and source lines, to reduce program disturb by aligning control gates and floating gates vertically and applying specific voltage gradients during programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MTP flash memory cell array is used with standard programming voltage application, then programming operation can be performed, but program disturb occurs to floating-gate transistors on the same page or different pages affecting endurance performance
Solution Approach 1:
The patent applies different voltage levels to different regions of the memory array during programming operations. Specifically, it applies a first voltage level to bit lines of a first page and a second voltage level to bit lines of a second page, creating localized voltage conditions that enable selective programming while preventing program disturb in non-target regions. This local differentiation of voltage quality resolves the contradiction by allowing programming functionality while eliminating harmful program disturb effects.
Solution Approach 2:
The patent changes the voltage parameter applied to bit lines based on the programming target. By dynamically adjusting the voltage level on bit lines (first voltage level for target page, second voltage level for non-target pages), the system enables precise control over electron injection, achieving successful programming of target cells while preventing unintended programming of non-target cells, thus resolving the program disturb issue.
2Productivity
If voltage is applied to program floating-gate transistor, then programming operation succeeds, but voltage difference causes program disturb to other transistors
Solution Approach 1:
The patent creates localized voltage conditions by applying different voltage levels to different bit lines simultaneously. The target bit line receives a first voltage level that enables successful programming, while non-target bit lines receive a second voltage level that prevents program disturb. This spatial differentiation of voltage quality ensures high programming success rate for target cells without causing harmful effects to other transistors.
Solution Approach 2:
The patent segments the bit line voltage application into distinct groups: target bit lines receive one voltage level while non-target bit lines receive another voltage level. This segmentation of voltage application allows independent control over programming operations on different pages, enabling successful programming of selected cells while isolating non-selected cells from program disturb effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively reduces program disturb in floating-gate transistors, enhancing the programming success rate and endurance of MTP flash memory cell arrays by minimizing unintended electron injection into non-target transistors.
Implementation Method 1
minimizing unintended electron injection into non-target transistors
Implementation Method 2
applying specific voltage gradients during programming operations
Data Source
AI summary
A flash memory cell array includes multiple flash memory units. A flash memory unit includes first and second select transistors, and first and second floating-gate transistors on a substrate. The first floating-gate transistor has a source connected to a drain of the first select transistor, and a drain connected to a drain of the second floating-gate transistor. The second floating-gate transistor has a source connected a drain of the second select transistor. The first and second floating-gate transistors of a flash memory unit in a j-th column have a control gate connected to a j-th word line. The first and second select transistors of the flash memory unit in the j-th column have a source connected to a common source line. The first and second floating-gate transistors of a flash memory unit in an i-th row have a drain connected to an i-th bit line.