MTP Memory Cell Capacitor Using STI Recess and Sidewall Doping
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Solution Overview
Problem
Multiple-Time Programming (MTP) memory cells require large capacitors to improve programming efficiency, leading to increased chip area occupancy.
Innovation Solution
The formation of coupling capacitors with a floating gate extending over active regions and STI regions, where the sidewalls of active regions are used to increase capacitance without expanding the chip area, by forming recesses in STI regions and doping the surface and sidewall portions of active regions to create a capacitor plate with enhanced capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large capacitors are used to improve programming efficiency of MTP memory cells, then programming efficiency is improved, but chip area occupancy increases
Solution Approach 1:
The patent utilizes the vertical dimension by extending the floating gate structure downward into the substrate to increase capacitor plate area. Instead of expanding the capacitor footprint horizontally on the chip surface, the design extends the capacitor plates vertically through deep trench formation and substrate penetration, effectively increasing capacitance without increasing chip area occupancy.
Solution Approach 2:
The patent nests the coupling capacitor structure within the memory cell structure by integrating the capacitor plates with the transistor structures. The floating gate serves dual purposes as both the control gate of the access transistor and the upper plate of the coupling capacitor, while the lower capacitor plate is formed in the substrate beneath the transistor, creating a nested configuration that maximizes space utilization.
2Adaptability or versatility
If additional process steps are incorporated into CMOS logic process to form MTP memory cells, then MTP memory cell functionality is achieved, but manufacturing complexity increases
Solution Approach 1:
The patent designs the floating gate structure to serve multiple functions: it acts as the control gate for the access transistor, the upper plate of the coupling capacitor, and provides the interface for charge storage. This multi-functionality reduces the need for separate dedicated structures, thereby simplifying the manufacturing process while achieving MTP functionality.
Solution Approach 2:
The patent merges the coupling capacitor formation process with the existing CMOS transistor fabrication steps. The same polysilicon deposition and patterning processes used to create the transistor gates are utilized to form the capacitor plates, and the isolation trenches serve dual purposes for both transistor definition and capacitor plate formation, thereby reducing the number of additional process steps required.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly increases the capacitance of coupling capacitors without increasing the chip area, allowing for efficient programming while maintaining compact memory cell design.
Implementation Method 1
The doped semiconductor region forms a lower capacitor plate of the coupling capacitor
Implementation Method 2
implanting a top surface layer and a side surface layer of the second active region to form an implantation region
Data Source
AI summary
A method includes forming Shallow Trench Isolation (STI) regions to separate a first active region and a second active region of a semiconductor substrate from each other, etching a portion of the STI regions that contacts a sidewall of the second active region to form a recess, and implanting a top surface layer and a side surface layer of the second active region to form an implantation region. The side surface layer of the second active region extends from the sidewall of the second active region into the second active region. An upper portion of the top surface layer and an upper portion of the side surface layer are oxidized to form a capacitor insulator. A floating gate is formed to extend over the first active region and the second active region. The floating gate includes a portion extending into the recess.