Multi-Time Programming Memory Cell Erase Inhibit Design
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Solution Overview
Problem
Conventional multi-time programming (MTP) memory cells lack the capability to perform an erase inhibit operation, limiting their functionality in memory arrays.
Innovation Solution
The MTP memory cell design includes a floating gate transistor, capacitors connected to an erase line, a control line, and an inhibit line, allowing for the implementation of erase inhibit operations by adjusting bias voltages, which enables selective program, program inhibit, erase, erase inhibit, and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional MTP memory cell structure is used, then the memory cell can perform program and erase operations, but it lacks erase inhibit capability
Solution Approach 1:
The gate structure is divided into multiple independent gate electrodes (first gate electrode, second gate electrode, third gate electrode, fourth gate electrode) that can be independently controlled. This segmentation allows different regions of the gate to perform different functions (program, erase, inhibit) simultaneously or selectively, enabling the memory cell to perform erase inhibit operations without requiring a completely new structure
Solution Approach 2:
The gate structure is designed to serve multiple functions through its segmented electrodes. The same gate structure can perform program operations, erase operations, and erase inhibit operations by applying different voltage combinations to different gate electrodes, eliminating the need for separate structures for each operation type
2Adaptability or versatility
If additional gate structures are added to enable erase inhibit operation, then erase inhibit capability is achieved, but device complexity increases
Solution Approach 1:
Multiple functional gates (program gate, erase gate, inhibit gate) are merged into a single integrated gate structure with multiple independently controllable electrodes. This consolidation allows the memory cell to achieve erase inhibit capability while avoiding the complexity of having completely separate gate structures for each function
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The enhanced MTP memory cell and array can perform erase inhibit operations, expanding their operational capabilities and improving data storage and retrieval efficiency.
Implementation Method 1
a first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line
Data Source
AI summary
A multi-time programming memory cell includes a floating gate transistor, a first capacitor, a second capacitor and a third capacitor. The floating gate transistor has a floating gate. A first terminal of the floating gate transistor is coupled to a source line. A second terminal of the floating gate transistor is coupled to a bit line. A first terminal of the first capacitor is connected with the floating gate. A second terminal of the first capacitor is connected with an erase line. A first terminal of the second capacitor is connected with the floating gate. A second terminal of the second capacitor is connected with a control line. A first terminal of the third capacitor is connected with the floating gate. A second terminal of the third capacitor is connected with an inhibit line.