MTP Memory Cell Structure with Integrated Control Capacitor
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Solution Overview
Problem
Existing Multi-Time Programmable (MTP) memory technologies face challenges with slow access time, small coupling ratio, and large cell size, often requiring additional processing steps and high junction band voltage for erasing operations.
Innovation Solution
A simple and cost-free MTP structure is developed using a non-volatile memory cell with a substrate, select and floating gates, a control gate coupled to a control capacitor, and an erase terminal decoupled from the control capacitor, optimized for efficient programming and reduced size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing MTP memory structures are used, then non-volatile memory functionality is achieved, but cell size becomes large
Solution Approach 1:
The patent merges the control gate and control capacitor into a single integrated structure. The control gate is formed over a control well and includes a capacitor formed within the control well, eliminating the need for separate capacitor structures. This integration significantly reduces the cell area while maintaining the non-volatile memory functionality through the coupled control gate-capacitor system.
2Reliability
If band-to-band tunneling hot hole (BBHH) erasing is used, then erasing operation is achieved, but high junction band voltage and additional process steps are required
Solution Approach 1:
The patent extracts the erasing function from the complex BBHH mechanism and implements it through a simplified trapped charge mechanism. By using a control capacitor coupled to the control gate, the erasing operation is achieved through conventional charge trapping and detrapping processes, eliminating the need for high junction band voltage and complex BBHH process steps while maintaining reliable erasing functionality.
3Reliability
If additional coupling erase gate and coupling capacitor are added, then erasing capability is improved, but area increases
Solution Approach 1:
The patent combines the control gate and control capacitor into an integrated structure where the control gate is formed over a control well containing the capacitor. This merged structure provides the necessary erasing capability through the control capacitor's coupling to the floating gate, eliminating the need for separate coupling erase gates and capacitors that would increase area.
4Reliability
If conventional MTP structures are used, then memory functionality is achieved, but access time is slow
Solution Approach 1:
The patent segments the memory cell into distinct functional regions with a select transistor and storage transistor arranged to enable independent control of programming and reading operations. The select transistor with its gate over the transistor well allows rapid channel control for fast access, while the storage transistor with floating gate maintains non-volatile functionality, achieving both speed and reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances programming efficiency, reduces the need for high voltage, and minimizes cell size, improving the performance and reliability of MTP memory cells while maintaining compatibility with the CMOS platform.
Implementation Method 1
A control gate is disposed over a control well. The control gate is coupled to the floating gate and includes a control capacitor.
Implementation Method 2
a first transistor having a select gate and a second transistor having a floating gate. The select and floating gates are adjacent to one another and disposed over a transistor well.
Data Source
AI summary
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. The memory cell includes a substrate, a first transistor having a select gate and a second transistor having a floating gate. The select and floating gates are adjacent to one another and disposed over a transistor well. The transistors include first and second S/D regions disposed adjacent to the sides of the gates. A control gate is disposed over a control well. The control gate is coupled to the floating gate and includes a control capacitor. An erase terminal is decoupled from the control capacitor and transistors.