MTP Memory Cell Structure with Coupled Gates
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Solution Overview
Problem
Existing multi-time programmable (MTP) memory technologies face challenges such as slow access time, small coupling ratio, and large cell size, often requiring additional processing steps and increased area for erasing operations, particularly with band-to-band tunneling hot hole methods.
Innovation Solution
A simple and cost-free MTP memory cell structure is developed using a substrate with first and second wells, featuring transistors with a select gate and a floating gate, and a control gate coupled to the floating gate, along with a metal-insulator-metal (MIM) capacitor, which enhances capacitive coupling and reduces the need for additional area and processing steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If band-to-band tunneling hot hole (BBHH) method is used for erasing operation, then erasing capability is achieved, but high junction band voltage and more process steps are required
Solution Approach 1:
The patent extracts the erasing function from the complex BBHH tunneling mechanism and implements it through a simpler hot carrier injection mechanism using the MTP memory cell structure with coupled control and floating gates. This eliminates the need for high junction band voltage and complex process steps while maintaining erasing capability.
Solution Approach 2:
The patent changes the physical mechanism from band-to-band tunneling to hot carrier injection by modifying the voltage application pattern on the control and floating gates. This parameter change transforms the erasing operation from a complex high-voltage process to a simpler low-voltage hot carrier injection process.
2Reliability
If additional coupling erase gate and coupling capacitor are added, then erasing operation is enabled, but area increases
Solution Approach 1:
The patent merges the control gate and floating gate into a coupled structure where the control gate is directly connected to the floating gate. This integration eliminates the need for separate coupling capacitors and erase gates, enabling erasing operation while maintaining compact cell area.
Solution Approach 2:
The control gate serves multiple functions: it controls the select transistor during read operations and simultaneously acts as the erase gate for erasing operations. This multi-functionality eliminates the need for dedicated erase gate structures and reduces overall cell area.
3Adaptability or versatility
If MTP memory structure is implemented, then customization capability is achieved, but additional processing steps are required
Solution Approach 1:
The patent segments the memory cell into distinct functional regions (select transistor, MTP memory cell with control gate and floating gate) that can be independently configured. This segmentation allows customization of memory parameters while using standard CMOS processing steps, avoiding the need for additional specialized processing.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed structure improves programming efficiency with increased capacitive coupling ratio and decoupled erase and programming paths, enhancing memory cell reliability and reducing wear and tear on the tunneling dielectric.
Implementation Method 1
The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and the second wells
Implementation Method 2
a capacitor having a metal-insulator-metal (MIM) capacitor being coupled to the floating gate
Data Source
AI summary
Embodiments of a simple and cost-free multi-time programmable (MTP) structure for non-volatile memory cells are presented. A non-volatile MTP memory cell includes a substrate, first and second wells disposed in the substrate, a first transistor having a select gate and a second transistor having a floating gate adjacent one another and disposed over the second well and sharing a diffusion region. The memory cell further includes a control gate disposed over the first well. The control gate is coupled to the floating gate and the control and floating gates include the same gate layer extending across the first and the second wells.