MTP Memory Inter-Gate Dielectric Edge Thicker Design
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Solution Overview
Problem
Multi-time programmable (MTP) memory devices face issues with data retention due to defects in the inter-gate dielectric layer between the control gate and the floating gate, leading to leakage current and reduced reliability.
Innovation Solution
The MTP memory design features an inter-gate dielectric layer with a thicker edge portion compared to the central portion of the floating gate, and a rounded top corner, which reduces leakage current and enhances data retention by preventing electrical field concentration and spike discharge.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the inter-gate dielectric layer is formed during growth processes of gate oxide layers, then the manufacturing process is integrated, but the thickness of the inter-gate dielectric layer becomes less than 150 angstroms leading to defects and leakage current
Solution Approach 1:
The inter-gate dielectric layer is formed preliminarily before the gate oxide layers are grown, ensuring that the dielectric layer is already in place and can be made sufficiently thick before subsequent processing steps. This preliminary formation allows for better quality control of the dielectric layer thickness and reduces defects.
Solution Approach 2:
The patent applies different thickness requirements to different regions of the inter-gate dielectric layer, with edges requiring greater thickness than central portions. This local quality approach ensures that critical areas with higher leakage risk have enhanced protection while maintaining overall device performance.
2Length of moving object
If the inter-gate dielectric layer thickness is kept thin for device miniaturization, then device size is reduced, but leakage current increases and reliability deteriorates
Solution Approach 1:
The patent implements non-uniform thickness distribution in the inter-gate dielectric layer, with thicker regions at edges and thinner regions in the center. This allows the overall device to be compact while critical edge regions maintain sufficient thickness to prevent leakage current and ensure reliability.
3Ease of manufacture
If conventional fabrication processes are used, then manufacturing is straightforward, but the inter-gate dielectric layer develops defects causing leakage current
Solution Approach 1:
The inter-gate dielectric layer is formed in advance before gate oxide growth, allowing sufficient time and process control to achieve high-quality, defect-free layers with appropriate thickness. This preliminary formation step ensures manufacturing precision is maintained while keeping the overall process integrated and straightforward.
Data Source
AI summary
A multi-time programmable (MTP) memory includes a tunneling dielectric layer, a floating gate, an inter-gate dielectric layer and a control gate. The tunneling dielectric layer is disposed on a substrate. The floating gate is disposed on the tunneling dielectric layer. The inter-gate dielectric layer is disposed on the floating gate, and a thickness of the inter-gate dielectric layer at edges of the floating gate is larger than a thickness of the inter-gate dielectric layer in a central portion of the floating gate. The control gate is disposed on the inter-gate dielectric layer.