Single-Transistor MTP Memory with Selective Gate Dielectric Programming
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Solution Overview
Problem
Current multi-time programmable (MTP) non-volatile memory devices face challenges with scaling, endurance/retention limits, high power consumption, complex structure, additional processing steps, and high cost, necessitating the development of area-efficient, low-power, high-speed, and reliable MTP memory compatible with CMOS processing and reduced manufacturing costs.
Innovation Solution
A semiconductor device with a single transistor MTP memory cell featuring a gate dielectric with different characteristics over first and second sub-regions, allowing for selective programming of a programmable resistive layer, reducing the need for complex structures and power consumption, and enabling multi-time programmability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If floating gate or charge trapping based MTP memory is used, then multi-time programmability is achieved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the programmable functionality from complex floating gate or charge trapping structures and concentrates it in a simple programmable resistive layer within the gate dielectric. This resistive layer can be programmed multiple times through resistance changes, achieving MTP functionality without the structural complexity of traditional approaches.
Solution Approach 2:
The patent utilizes changes in resistance parameters of the programmable resistive layer to achieve multi-time programmability. By controlling the resistance state of this layer through applied voltages, the memory can be programmed and re-programmed multiple times, providing adaptability without increasing structural complexity.
2Reliability
If conventional MTP memory structures are used, then non-volatile storage is achieved, but area efficiency decreases
Solution Approach 1:
The patent merges the storage functionality into the gate dielectric structure itself by incorporating a programmable resistive layer within the gate stack. This integration eliminates the need for separate storage elements, achieving non-volatile storage in a compact area-efficient single-transistor configuration.
Solution Approach 2:
The gate dielectric structure serves multiple functions simultaneously: it acts as the gate insulator, contains the programmable resistive layer for storage, and enables multi-time programmability. This multi-functionality reduces the overall area requirement while maintaining non-volatile storage capability.
3Adaptability or versatility
If MTP memory is implemented with traditional approaches, then programmability is achieved, but power consumption increases
Solution Approach 1:
The patent applies local quality by creating different regions within the gate dielectric: a programmable resistive layer that can be modified through programming, and a non-programmable region that maintains stable electrical characteristics. This localized programming capability reduces the energy required for programming operations compared to global restructuring approaches.
4Device complexity
If simplified MTP structures are used, then manufacturing cost is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent controls the programming precision by carefully managing the resistance parameter changes in the programmable resistive layer. Through controlled voltage application and timing, the resistance can be adjusted to specific states with high precision, ensuring reliable data storage despite the simplified structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced area requirements, lower operating voltages, improved reproducibility of filaments, and simplified manufacturing, resulting in a more efficient and cost-effective MTP memory solution compatible with CMOS processing.
Implementation Method 1
a programmable resistive layer... when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming
Data Source
AI summary
Devices and methods for forming a device are presented. The device includes a substrate having a device region and first and second isolation regions surrounding the device region. The device includes a multi-time programmable (MTP) memory cell having a single transistor disposed on the device region. The transistor includes a gate having a gate electrode over a gate dielectric which includes a programmable resistive layer. The gate dielectric is disposed over a channel region having first and second sub-regions in the substrate. The gate dielectric disposed above the first and second sub-regions has different characteristics such that when the memory cell is programmed, a portion of the programmable resistive layer above one of the first or second sub-region is more susceptible for programming relative to portion of the programmable resistive above the other first or second sub-region.