MTP Memory Cell With Shared Junction Gates
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Solution Overview
Problem
Existing non-volatile multi-time programmable (MTP) memories face challenges with long operation times, small coupling ratios, large cell sizes, and the need for different voltage values at various terminals, which complicates their integration and increases processing steps, especially when trying to be compatible with the standard CMOS platform.
Innovation Solution
A non-volatile MTP memory cell structure is developed, comprising a substrate with a transistor well, control and erase capacitor wells, and control and erase gates, where the control and erase gates share a common junction configuration, allowing for simplified voltage requirements and reduced terminal voltages, and a method for forming this cell that involves specific doping and well configurations to enhance performance and compatibility with CMOS technology.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If conventional MTP memory structures are used, then non-volatile storage functionality is achieved, but operation time per cycle becomes long
Solution Approach 1:
The memory cell is segmented into distinct functional regions: a transistor well for charge storage, a control well for programming operations, and an erase well for erasure operations. This segmentation allows independent optimization of each region's function, enabling faster programming and erasing speeds while maintaining non-volatile storage capability.
Solution Approach 2:
Capacitor structures are introduced as intermediary elements between the transistor well and the control/erase gates. These capacitors enhance the coupling ratio and enable more efficient charge transfer during programming and erasing operations, thereby reducing operation time per cycle without sacrificing storage functionality.
2Quantity of substance
If conventional MTP memory structures are used, then non-volatile storage functionality is achieved, but cell size becomes large
Solution Approach 1:
The control well and erase well are nested within or adjacent to the transistor well structure, with capacitor structures integrated into the same vertical space. This nested configuration allows multiple functional elements to share overlapping spatial regions, significantly reducing the overall cell footprint while maintaining adequate storage capacity.
Solution Approach 2:
The patent utilizes vertical stacking of wells and gates in the third dimension rather than spreading all components horizontally. The transistor well, control well, and erase well are arranged in a vertical configuration with corresponding gates stacked above them, transforming a planar layout into a three-dimensional structure that increases storage density without expanding cell area.
3Adaptability or versatility
If conventional MTP memory structures are used, then non-volatile storage functionality is achieved, but different voltage values are required at various terminals
Solution Approach 1:
The control gate and erase gate share a common junction configuration and can be controlled by a unified voltage signaling scheme. The capacitor-coupled architecture allows the same control terminal to perform both programming and erasing functions by applying different voltage levels, eliminating the need for separate voltage supplies for different operations and simplifying the overall voltage requirement structure.
4Reliability
If conventional MTP memory structures are used, then non-volatile storage functionality is achieved, but coupling ratio becomes small
Solution Approach 1:
Capacitor structures are positioned as intermediary elements between the transistor well and the control/erase gates. These capacitors provide strong electrical coupling that enhances charge transfer efficiency during programming and erasing operations, thereby improving the coupling ratio and charge retention reliability.
5Reliability
If conventional MTP memory structures are used, then non-volatile storage functionality is achieved, but additional processing steps are required
Solution Approach 1:
The control well and erase well fabrication processes are merged into a single processing sequence, with both wells formed using the same doping and patterning steps. The capacitor structures for both wells are created simultaneously, and the control and erase gates are formed in a unified process flow, thereby reducing the total number of additional processing steps required compared to conventional separate well structures.
Data Source
AI summary
Device and methods for forming a single transistor non-volatile (NV) multi-time programmable (MTP) memory cell are disclosed. The disclosed memory cell is derived via the disclosed method that includes providing a substrate and forming at least a transistor well with a second polarity type dopant and first and second capacitor wells with a first polarity type dopant in the substrate. The method also includes forming a transistor having a floating gate over the transistor well, a control gate over the first capacitor well and coupled to the floating gate, an erase gate over the second capacitor well and coupled to the floating gate. The control gate comprises a control capacitor while the erase gate comprises an erase capacitor that is decoupled from the control capacitor.