Multi-Time Programmable NVM via Self-Aligned Contacts

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Solution Overview

Problem

Existing multi-time programmable (MTP) non-volatile memory (NVM) solutions require additional masking steps and process complexity, leading to increased costs, which is a challenge for fabricating low-cost MTP NVM.

Innovation Solution

A self-aligned contact (SAC) methodology is used to form a select gate and a floating gate above a substrate, with pairs of SACs on opposite sides of a doped region, electrically connected to a metal layer, and additional spacers and hardmasks are formed to enable low-cost MTP NVM production.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If dual poly-gate NVM or charge-trapping type poly-silicon-oxide-silicon nitride-oxide-silicon (SONOS) NVM is used to achieve multi-time programmability, then the device can be updated multiple times, but additional masking steps and process complexity are required, which increases cost

Engineering Contradiction:
Improvemulti-time programmabilityVSAvoidprocess complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent extracts the self-aligned contact formation process from the conventional fabrication sequence and positions it to occur before floating gate formation. This reordering eliminates the need for additional masking steps that would otherwise be required to achieve multi-time programmability, thereby reducing process complexity while maintaining the ability to program the device multiple times

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The self-aligned contacts are formed in advance, before the floating gate is created. This preliminary action establishes the contact structure early in the fabrication process, allowing subsequent layers to be formed without requiring additional alignment masks, thus simplifying the overall manufacturing process while enabling MTP functionality

Inventive Principle:
Principle #10Preliminary action

2Adaptability or versatility

If dual poly-gate NVM or charge-trapping type poly-silicon-oxide-silicon nitride-oxide-silicon (SONOS) NVM is used to achieve multi-time programmability, then the device can be updated multiple times, but additional masking steps and process complexity are required, which increases cost

Engineering Contradiction:
Improvemulti-time programmabilityVSAvoidmanufacturing cost
Core Design Contradiction:
Adaptability or versatilityVSEase of manufacture

Solution Approach 1:

The patent removes the need for additional masking steps by extracting and repositioning the self-aligned contact formation process. This eliminates expensive photolithography mask steps that would otherwise be required to achieve multi-time programmability, directly reducing manufacturing costs while maintaining MTP capability

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

By forming self-aligned contacts before the floating gate, the patent performs a preliminary action that eliminates the need for subsequent costly masking operations. This early structuring reduces the total number of fabrication steps and associated material costs, making MTP NVM more economically viable

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8772108B1Multi-time programmable non-volatile memory
Publication Date: 2014.07.08 GLOBALFOUNDRIES SINGAPORE PTE LTD
  • US8772108B1 patent drawing
  • US8772108B1 patent drawing
  • US8772108B1 patent drawing

AI summary

A process for creating a low-cost multi-time programmable (MTP) non-volatile memory (NVM) and the resulting device are provided. Embodiments include forming a select gate and a floating gate above a substrate, each over a first shallow trench isolation (STI) region, a doped region formed between a source and a drain, and a second STI region, forming a metal layer over the floating gate, and forming a pair of self-aligned contacts on the first and second STI regions on opposite sides of the doped region, respectively, and electrically connected to the metal layer.