MTP PMOS Floating Gate Memory Cell Withstand High Voltage Erase
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Solution Overview
Problem
Existing multiple time programmable (MTP) memory devices are limited by the need for high positive erase voltages, which existing technologies cannot effectively handle, especially for CMOS technologies using 5V I/O devices with gate dielectric thickness in the 10-15 nm range requiring 12V to 18V erase voltages.
Innovation Solution
The proposed MTP memory cell design includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor, with specific configurations such as gate oxide layers of 10-15 nm thickness, extended drain isolation, and silicide layers to withstand higher erase voltages, allowing for programming, inhibition, reading, and erasing of logic states using combinations of voltages applied to the terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high positive erase voltages (12V to 18V) are applied to erase memory cells in CMOS technologies with 10-15 nm gate oxide, then erase operation is enabled, but gate oxide breakdown occurs
Solution Approach 1:
The patent segments the voltage stress by introducing an intermediate n-well between the high voltage terminal and the gate oxide. The n-well capacitor structure divides the voltage path, allowing the high positive erase voltage to be applied to the n-well rather than directly to the gate oxide, thus protecting the gate oxide from breakdown while enabling the erase operation.
Solution Approach 2:
The n-well acts as an intermediary structure that mediates between the high voltage erase signal and the sensitive gate oxide. By applying the high positive voltage to the n-well and using the n-well capacitor for the erase operation, the gate oxide is protected from direct exposure to breakdown voltages, enabling safe erase operations in thicker gate oxide technologies.
2Ease of operation
If thin gate oxide (less than 10 nm) is used to reduce erase voltage requirements, then lower voltage operations are enabled, but manufacturing precision and device scaling are limited
Solution Approach 1:
The patent enables dynamic voltage handling capability by designing the memory cell with an n-well capacitor and high voltage transistor configuration. This allows the device to dynamically switch between handling low voltages during normal operation and withstanding high positive voltages during erase operations, providing voltage flexibility without being constrained by fixed gate oxide thickness requirements.
Solution Approach 2:
The invention changes the voltage parameter handling capability by introducing the n-well capacitor structure. This allows the same memory cell design to operate with thicker gate oxides (10-15 nm) that require higher erase voltages, rather than being locked into thin gate oxide designs, thus enabling parameter adaptation to different process technologies.
3Adaptability or versatility
If existing MTP memory cell structures are used with 5V I/O devices, then standard CMOS compatibility is maintained, but high positive erase voltages cannot be withstood
Solution Approach 1:
The patent achieves universality by designing a memory cell structure that serves multiple functions: it maintains compatibility with standard CMOS fabrication processes while simultaneously providing the capability to withstand high positive erase voltages. The n-well capacitor and high voltage transistor configuration enable the same cell structure to be used across different voltage domains, from standard 5V I/O devices to high-voltage erase operations.
Solution Approach 2:
The invention uses a composite structure combining n-well, gate oxide, and polysilicon layers to create the n-well capacitor. This composite material approach allows the structure to handle high positive voltages during erase operations while maintaining compatibility with standard CMOS processes, effectively merging the benefits of thick gate oxide protection with high-voltage erase capability in a single integrated structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables MTP memory cells to withstand high positive erase voltages, overcoming the limitations of existing technologies by allowing for efficient programming and erasure operations in CMOS technologies with thicker gate oxides, thus expanding the applicability to devices with higher I/O voltages.
Implementation Method 1
a floating gate PMOS transistor... The floating gate PMOS transistor can store a logic state
Implementation Method 2
The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell
Implementation Method 3
Alternatively, an erase operation can be accomplished by application of the high positive voltage to the n-well housing the floating gate device
Data Source
AI summary
A multiple time programmable (MTP) memory cell, in accordance with an embodiment, includes a floating gate PMOS transistor, a high voltage NMOS transistor, and an n-well capacitor. The floating gate PMOS transistor includes a source that forms a first terminal of the memory cell, a drain and a gate. The high voltage NMOS transistor includes a source connected to ground, an extended drain connected to the drain of the PMOS transistor, and a gate forming a second terminal of the memory cell. The n-well capacitor includes a first terminal connected to the gate of the PMOS transistor, and a second terminal forming a third terminal of the memory cell. The floating gate PMOS transistor can store a logic state. Combinations of voltages can be applied to the first, second and third terminals of the memory cell to program, inhibit program, read and erase the logic state.