Multi-threaded Processor Memory Controller Architecture
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Solution Overview
Problem
Multi-threaded processors face challenges with direct memory operations due to high latencies, instruction cache misses, memory bandwidth utilization, and efficient implementation of reduction operations, particularly in concurrent processing environments like graph analytics workloads.
Innovation Solution
The proposed system architecture for multi-threaded processors includes dual-memory operations, a direct memory access engine, optimized instruction cache management, dynamic memory interleaving, and hardware support for reduction operations to address these challenges, enhancing memory transactions and throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If direct memory operations are used to move data between memory locations, then data transfer capability is improved, but latency increases significantly due to returning each datum to the requesting core pipeline
Solution Approach 1:
The patent introduces a memory controller as an intermediary component that directly transfers data between memory locations without routing through the core pipeline. The memory controller includes a dual-port buffer that enables direct memory-to-memory operations, eliminating the latency penalty of returning data to the requesting core while maintaining high data transfer capability.
Solution Approach 2:
The memory controller is segmented into multiple independent functional units including a dual-port buffer, address generation unit, and control logic. This segmentation allows parallel processing of multiple memory operations simultaneously, improving overall data transfer throughput while managing latency through pipelined operation of individual segments.
2Productivity
If multiple threads concurrently access a common instruction cache, then processing parallelism is improved, but cache miss handling becomes more complex and creates pressure points
Solution Approach 1:
The patent extends the traditional single-dimension cache access model to multiple dimensions by implementing a multi-threaded cache architecture where each thread has its own cache tag array and data array. This dimensional expansion allows simultaneous cache operations from multiple threads without interference, reducing miss handling complexity while maintaining high parallelism.
Solution Approach 2:
The patent creates copies of critical cache structures for each thread, including separate tag arrays and data arrays. This copying approach allows each thread to independently manage its cache operations without contention, simplifying miss handling logic while enabling efficient concurrent access from multiple threads.
3Productivity
If memory accesses are striped across multiple memory channels, then memory bandwidth utilization is improved, but address management complexity increases
Solution Approach 1:
The patent implements dynamic address striping where the memory controller automatically selects and switches between different striping patterns based on current workload characteristics. The address generation unit can dynamically reconfigure which bits of the memory address are used for channel selection, allowing adaptive optimization of bandwidth utilization without fixed complex address management.
Solution Approach 2:
The patent changes the parameter of address striping from a fixed configuration to a dynamically adjustable parameter. The memory controller can modify striping granularity, number of active channels, and address bit selection based on real-time performance metrics, simplifying address management while maintaining optimal bandwidth utilization through parameter adaptation.
4Productivity
If multiple concurrent outstanding memory requests are issued, then memory throughput is improved, but hardware tracking complexity increases
Solution Approach 1:
The patent implements preliminary ordering and tagging of memory requests before they are issued to the memory subsystem. The address generation unit pre-assigns unique identifiers and priority levels to each outstanding request, and maintains an ordered queue of pending operations. This preliminary organization simplifies the tracking hardware by providing structured request metadata that enables efficient matching of responses to requests without complex arbitration logic.
Data Source
AI summary
Disclosed embodiments relate to an improved memory system architecture for multi-threaded processors. In one example, a system includes a system comprising a multi-threaded processor core (MTPC), the MTPC comprising: P pipelines, each to concurrently process T threads; a crossbar to communicatively couple the P pipelines; a memory for use by the P pipelines, a scheduler to optimize reduction operations by assigning multiple threads to generate results of commutative arithmetic operations, and then accumulate the generated results, and a memory controller (MC) to connect with external storage and other MTPCs, the MC further comprising at least one optimization selected from: an instruction set architecture including a dual-memory operation; a direct memory access (DMA) engine; a buffer to store multiple pending instruction cache requests; multiple channels across which to stripe memory requests; and a shadow-tag coherency management unit.