MuGFET Array Layout with Odd Fin Transistors
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Solution Overview
Problem
Current multi-gate field effect transistor (MuGFET) technologies face challenges in reducing the core cell area due to constraints in fin pitch and the inability to form transistor stacks with an odd number of fins, leading to inefficient use of chip area, especially for single fin devices.
Innovation Solution
The use of spacer or alternating phase shift regions to form small-pitched fins, allowing for the fabrication of SRAM cells with single-fin PMOS and NMOS devices, and replicating these layouts to create efficient arrays with shared source and drain regions, enabling the formation of odd-numbered fin transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If multiple sacrificial spacers are formed to achieve small fin pitch, then fin pitch is reduced, but only even number of fins can be formed
Solution Approach 1:
The patent extracts the constraint of using only sacrificial spacers by introducing alternating phase shift regions as an additional method for defining fins. This allows fins to be formed in locations not constrained by spacer structures, enabling odd-numbered fin configurations while maintaining small fin pitch achieved through spacer-based even-numbered fins.
2Adaptability or versatility
If single fin devices are fabricated using additional clean-out steps, then single fin transistors can be formed, but chip area efficiency decreases
Solution Approach 1:
The patent uses alternating phase shift regions that can be replicated across the chip to define fins. This copying approach allows single-fin devices to be formed directly through the phase shift mask pattern without requiring additional clean-out steps, as the phase shift regions can be precisely positioned to create the desired fin configurations including single-fin structures.
3Adaptability or versatility
If complex clean-out steps are used for single fin devices, then single fin transistors can be formed, but manufacturing complexity increases
Solution Approach 1:
The patent segments the fin formation process into two independent methods: sacrificial spacers for even-numbered fins and alternating phase shift regions for odd-numbered fins including single-fin devices. This segmentation allows each method to be optimized independently, eliminating the need for complex clean-out steps and reducing overall fabrication process complexity.
Data Source
AI summary
A circuit array includes a plurality cells, wherein each cell has at least one group of odd fins. The cells may be arranged in a repeating pattern that includes mirror images of the pattern. A plurality of fin forming regions are provided about which the fins are formed for the dual fin and single fin transistors.


