MUGFET Replacement Gate Structure for Leakage Control
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Solution Overview
Problem
The widespread implementation of multi-gate field effect transistors (MUGFETs) is hindered by manufacturability challenges, including lithography and patterning processes, as well as high parasitic source/drain resistance and increased 'off-state' leakage current, which affects power consumption and device performance.
Innovation Solution
A dual damascene replacement gate structure is fabricated by forming temporary spacer gates around active regions, depositing a dielectric material, etching to expose the spacer gates, removing them to create spaces, and filling these spaces with gate material, resulting in a non-planar structure that straddles fins and reduces gate-to-source/drain capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional planar MUGFET structures are used, then manufacturing process simplicity is maintained, but off-state leakage current increases and short channel effects worsen at 32 nm scale
Solution Approach 1:
The patent transitions from a planar gate structure to a three-dimensional wrap-around gate structure that surrounds the channel on multiple sides. This dimensional change enables superior electrostatic control and reduced off-state leakage current by controlling the channel from multiple directions, while the self-aligned fabrication process manages the increased structural complexity.
Solution Approach 2:
The gate structure is segmented into multiple portions that wrap around different sides of the channel region. These segmented gate portions are formed through sequential patterning and etching steps, allowing independent optimization of each gate section while collectively achieving enhanced channel control and reduced leakage.
2Productivity
If non-planar MUGFET structures with fins are used, then transistor density and drive current are enhanced, but fabrication complexity increases and parasitic capacitance between fins increases
Solution Approach 1:
The patent forms sacrificial mandrels and spacer structures beforehand to define the fin and gate geometries. The wrap-around gate is constructed using preliminary sacrificial elements that are later removed, enabling complex three-dimensional gate structures to be formed through sequential deposition and etching steps without requiring direct complex patterning of the final gate shape.
Solution Approach 2:
Sacrificial mandrels and spacer materials serve as intermediary structures during fabrication. These temporary elements mediate the formation of the final fin and gate structures by providing placeholders that guide subsequent deposition and etching processes, simplifying the overall fabrication sequence despite the complexity of the final non-planar structure.
3Loss of energy
If conventional gate structures are used, then manufacturing process simplicity is maintained, but parasitic capacitance between gate and source/drain regions increases
Solution Approach 1:
The patent implements local spacing variations by positioning dielectric material at specific locations between the gate and source/drain regions. This local quality adjustment reduces parasitic capacitance precisely where needed at the gate-to-source/drain interfaces, while maintaining simpler manufacturing processes through targeted material deposition rather than global structural changes.
Data Source
AI summary
A MUGFET and method of manufacturing a MUGFET is shown. The method of manufacturing the MUGFET includes forming temporary spacer gates about a plurality of active regions and depositing a dielectric material over the temporary spacer gates, including between the plurality of active regions. The method further includes etching portions of the dielectric material to expose the temporary spacer gates and removing the temporary spacer gates, leaving a space between the active regions and a remaining portion of the dielectric material. The method additionally includes filling the space between the active regions and above the remaining portion of the dielectric material with a gate material.