MUL-MAC Unit Register Sharing for Power Reduction
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Solution Overview
Problem
Existing multiply-accumulate units in processor cores are expensive due to the need for additional registers and wiring, and they incur significant delay, which affects processor performance, especially in digital signal processing and video/graphics applications.
Innovation Solution
A MUL-MAC unit that uses a single register for holding results and acts as an accumulator, allowing selective implementation of multiply and multiply-accumulate instructions through a multiplier, addition circuitry, and accumulator circuitry controlled by an accumulate signal, eliminating the need for redundant registers and optimizing hardware sharing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a third register is added to hold the third operand for MAC operations, then the multiply-accumulate operation can be implemented, but the register file size increases and wiring complexity increases
Solution Approach 1:
The result register is designed to serve dual purposes: storing multiplication results for MUL operations and acting as an accumulator for MAC operations. The accumulator circuitry shares the same physical register resource, eliminating the need for a separate third register. This multi-functionality reduces the register file size and wiring complexity while maintaining MAC operation capability.
Solution Approach 2:
The patent merges the accumulator function into the existing result register by adding accumulator circuitry that can selectively accumulate or not accumulate based on the accumulate control signal. This combination of functions within a single register eliminates the need for additional register resources and reduces overall device complexity.
2Adaptability or versatility
If additional registers and wiring are added for MAC operations, then multiply-accumulate functionality is achieved, but power consumption increases
Solution Approach 1:
By making the result register universal for both MUL and MAC operations through shared accumulator circuitry, the patent eliminates the need for additional register resources that would consume extra power. The same physical register and wiring infrastructure is reused, reducing overall power consumption while maintaining MAC functionality.
3Adaptability or versatility
If a third register is provided for the third operand, then MAC instructions can be implemented, but the unit becomes unduly expensive
Solution Approach 1:
The result register is designed to universally handle both multiplication results and accumulator values. The accumulator circuitry is integrated into the existing register structure, allowing the same hardware to perform both MUL and MAC operations without requiring additional expensive register resources or complex wiring.
4Adaptability or versatility
If additional registers are added for MAC operations, then the operation can be implemented, but the delay increases
Solution Approach 1:
By merging the accumulator function into the result register with shared circuitry, the patent reduces the number of signal propagation paths and eliminates additional register stages that would increase delay. The integrated design allows for faster operation while maintaining MAC functionality.
Data Source
AI summary
An arithmetic unit for selectively implementing one of a multiply and multiply-accumulate instruction, including a multiplier, addition circuitry, a result register, and accumulator circuitry. The multiplier arranged to receive first and second operands and operable to generate multiplication terms. The addition circuitry for receiving multiplication terms from the multiplier and operable to combine them to generate a multiplication result. The result register for receiving the multiplication result from the adder. The accumulator circuitry connected to receive a value stored in the result register and an accumulate control signal which determines whether the arithmetic unit implements a multiply or a multiply-accumulate instruction.