Multi-Accelerator Control Data Flow Without CPU Transfer Overhead

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Solution Overview

Problem

Conventional accelerator systems face challenges in increasing the speed of real-time processing due to CPU-controlled inter-accelerator communication, which leads to overhead and reduced scalability, especially when multiple accelerators are used.

Innovation Solution

An accelerator control system that utilizes an accelerator control device and accelerators with autonomous metadata handling, allowing accelerators to perform arithmetic processing and data transfer without CPU intervention, reducing overhead and enabling asynchronous operation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the CPU controls data transfer between accelerators, then the arithmetic processing can be completed, but the processing speed decreases due to overhead from exclusive control, interruption notification, and synchronous control

Engineering Contradiction:
Improvearithmetic processing speedVSAvoidoverhead time
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The transfer destination accelerator autonomously determines whether to perform arithmetic processing by checking for the presence of control data in its local storage, without requiring CPU intervention. The accelerator independently acquires control data from storage, performs arithmetic processing, and stores results, enabling self-service operation that eliminates CPU control overhead.

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The invention extracts the control function from the CPU and transfers it to the accelerator itself. The accelerator now independently handles control data acquisition, arithmetic processing determination, and result storage, separating these functions from CPU control and eliminating the overhead associated with CPU-managed inter-accelerator communication.

Inventive Principle:
Principle #2Taking out (Extraction)

2Productivity

If a large number of accelerators are used, then processing capacity increases, but direct data transfer becomes impossible due to bus specifications, reducing scalability

Engineering Contradiction:
Improveprocessing capacityVSAvoidscalability
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The invention segments the control data into individual accelerator-specific data structures stored in each accelerator's local storage. Each accelerator independently manages its own control data, allowing the system to scale to many accelerators without requiring complex centralized bus control, as each accelerator operates autonomously based on its local control information.

Inventive Principle:
Principle #1Segmentation

3Ease of operation

If the CPU transmits control signals for data transfer, then data communication between accelerators is driven, but the system complexity increases due to multiple control signal transmissions

Engineering Contradiction:
Improvedata communication controlVSAvoidcontrol signal transmission complexity
Core Design Contradiction:
Ease of operationVSDevice complexity

Solution Approach 1:

The control data is prepared in advance and stored in the transfer destination accelerator's storage before arithmetic processing begins. This preliminary preparation eliminates the need for multiple real-time control signal transmissions during data transfer, as the accelerator simply retrieves pre-prepared control data and executes autonomously.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS12524244B2Accelerator control system using control data to perform arithmetic processing on a plurality of accelerators
Publication Date: 2026.01.13 NT T INC
  • US12524244B2 patent drawing
  • US12524244B2 patent drawing
  • US12524244B2 patent drawing

AI summary

An accelerator control system includes an accelerator control device and a plurality of accelerators, wherein the accelerator control device includes first processing circuitry configured to store control data including a location of data which is an arithmetic processing target, information on an accelerator for performing arithmetic processing, and information specifying content of the arithmetic processing of the accelerator, and determine completion of the arithmetic processing by the accelerator when the control data which has been subjected to the arithmetic processing by the accelerator is stored in a storage, and each of the accelerators includes second processing circuitry configured to acquire the control data from the storage, and perform arithmetic processing on the data which is an arithmetic processing target according to the location of the data which is an arithmetic processing target and information specifying the content of the arithmetic processing of the accelerator included in the acquired control data.