Multi-Access Memory Controller for Graph Data Structures
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Solution Overview
Problem
Current methods, such as cache and prefetching, struggle to optimize access performance for data structures like graphs in big data applications, leading to numerous random memory accesses that hinder computer system performance.
Innovation Solution
A method and apparatus for multi-access in memory that receives non-contiguous addresses, performs predetermined operations, and outputs results, potentially using a buffer area to store intermediate results, allowing for improved access speed and efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If cache or prefetching methods are used to reduce random memory accesses, then memory access performance is improved, but these methods cannot effectively optimize graph data structures which still require numerous random accesses
Solution Approach 1:
The patent segments the memory access process into multiple independent parallel access channels. Each channel can independently access different memory addresses simultaneously, allowing graph data structures with scattered vertices to be accessed in parallel rather than sequentially, thus resolving the limitation of traditional cache/prefetching methods on graph data optimization
Solution Approach 2:
The patent creates a universal multi-access memory interface that can handle both traditional sequential access patterns and graph data structure access patterns. The memory controller is designed to support multiple access types (continuous and non-contiguous addresses) through the same hardware interface, making it adaptable to various data structures including graphs while maintaining good performance
2Productivity
If one memory access is performed at a time, then memory operations are simple, but data processing speed is slow and access time is long
Solution Approach 1:
The patent merges multiple memory access operations into a single unified multi-access command. Instead of executing N separate read/write operations for N different addresses, the system combines them into one atomic operation that accesses multiple addresses simultaneously, thereby increasing data processing speed while keeping the operation interface relatively simple
Solution Approach 2:
The patent ensures continuous useful action by enabling parallel memory access across multiple addresses simultaneously. While traditional systems must complete one access before starting the next, this invention maintains continuous productive work by utilizing multiple memory banks or access channels in parallel, eliminating idle time between sequential accesses
Data Source
AI summary
Provided are a method for multiple accesses in a memory, an apparatus supporting multiple accesses in the memory and a storage system. The method comprises: receiving a number N of addresses in the memory, wherein N is an integer larger than 1 and the number N of addresses are discontinuous; performing a preset operation according to the number N of addresses; and outputting the result of the operation. As a consequence, the performances of a computer system can be improved, and a user can input and use the desired addresses just as required by the user.