Multi-access Memory Modules with Data Buffer and Multiplexer Devices
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Solution Overview
Problem
Current memory systems face limitations in memory module slots and expansion capabilities, necessitating efficient communication methods to maximize functionality and capacity without overutilizing fixed resources.
Innovation Solution
The implementation of data buffer and multiplexer devices, registered clock drivers, and data conversion modules that enable communication between a host memory controller and multiple memory modules, allowing for simultaneous access and doubling of memory bandwidth by converting parallel data signals to serial and back, effectively utilizing existing resources more efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory modules are connected to a host memory controller through fixed memory module slots and serial computer expansion bus slots, then memory capacity and functionality are limited, but adding more slots and expansion capabilities increases device complexity
Solution Approach 1:
The patent implements a universal interface where a single memory module can function as both a local memory device and a remote memory device over a serial computer expansion bus. The same physical hardware (memory module, data buffer, multiplexer) serves multiple purposes: direct access when connected to memory slot, and remote access when connected to expansion bus, eliminating the need for separate dedicated slots for different memory types
Solution Approach 2:
The patent introduces data buffer and multiplexer devices as intermediaries between the host memory controller and memory modules. These intermediaries manage the communication protocols, handle signal conversion between parallel and serial interfaces, and coordinate access to multiple memory modules, thereby reducing the overall system complexity while enabling expanded memory capacity
2Speed
If data signals are transmitted at high clock rates from host memory controller to memory modules, then data transfer speed is improved, but signal integrity and timing synchronization become more difficult to maintain
Solution Approach 1:
The data buffer and multiplexer devices serve as intermediaries that receive high-speed parallel data signals from the host memory controller and convert them to serial signals for transmission over the expansion bus. This conversion process manages signal integrity by serializing high-frequency signals, reducing electromagnetic interference and timing sensitivity while maintaining data transfer rate through efficient parallel-to-serial conversion
Solution Approach 2:
The patent changes the signal transmission parameter from parallel high-speed to serial lower-speed transmission. By converting parallel data signals to serial signals, the system can maintain reliable signal integrity at lower frequencies while achieving high data transfer rates through multiple parallel channels operating in parallel, effectively managing the trade-off between speed and reliability
3Adaptability or versatility
If parallel data signals are converted to serial signals for communication over serial computer expansion bus, then compatibility with existing expansion buses is improved, but data conversion complexity and processing time increase
Solution Approach 1:
The patent merges the data conversion functionality directly into the data buffer and multiplexer devices that are already present in the memory module interface. Rather than adding separate conversion hardware, the existing data buffer integrates both buffering and parallel-to-serial conversion functions, reducing overall system complexity while maintaining compatibility with serial expansion buses
Solution Approach 2:
The data buffer and multiplexer devices perform self-service by handling their own data conversion tasks without requiring external processing. The multiplexer devices automatically manage the parallel-to-serial conversion as part of their normal operation, eliminating the need for separate conversion processing steps and reducing overall system complexity
Data Source
AI summary
An apparatus includes a plurality of data buffer and multiplexer devices that communicate data signals with the host memory controller at twice the clock rate that the data buffer and multiplexer devices communicate first and second data signals with first and second memory modules. The apparatus further includes a registered clock driver that communicates host command and address signals at twice the clock rate that the registered clock driver communicates first and second command and address signals with the first and second memory modules. The second data signals and second command and address signals may be directed to a data conversion module that converts the signals to be communicated over a serial computer expansion bus with the second memory module.