Multi-Axial Buffer Circuitry for Vector Data Transfer

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Solution Overview

Problem

Existing data processing systems face inefficiencies in transferring data structures between memory and register banks, particularly in vector operations, requiring a significant number of accesses to memory and register banks to gather and scatter data elements, which hinders performance.

Innovation Solution

The implementation of a multi-axial buffer circuitry with an array of storage elements organized in sets and groups, allowing data elements to be stored and retrieved based on identifiers, enabling efficient construction and storage of vectors in parallel, reducing memory and register bank accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data structures are transferred directly between memory and register bank using conventional techniques, then data element gathering can be performed, but a significant number of memory and register bank accesses are required which reduces performance

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoidnumber of memory accesses
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

A multi-axial buffer is introduced as an intermediary component between memory and the register bank. This buffer contains an array of storage elements organized in N sets along a first axis and VL groups along a second axis, enabling efficient reorganization of data structures. The buffer receives data structures from memory, stores them in appropriate groups based on identifiers, and then outputs the reorganized data to the register bank, significantly reducing the total number of accesses required.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The buffer employs a two-dimensional array structure with N sets along the first axis and VL groups along the second axis. This multi-axial organization allows data structures to be stored and retrieved along different dimensions, enabling parallel construction of multiple vectors simultaneously. The dimensional reorganization transforms the data access pattern from sequential to parallel, improving transfer efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Reliability

If multiple data structures are accessed to form vector operands, then complete vector data can be assembled, but the number of access operations increases which affects energy efficiency

Engineering Contradiction:
Improvevector data completenessVSAvoidenergy consumption of data access operations
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The buffer merges multiple data structure accesses into a single unified buffer operation. By storing multiple data structures in the buffer's array structure and then retrieving them in the desired vector format, the system combines what would otherwise be multiple separate memory-to-register transfers into more efficient buffered operations, reducing overall energy consumption.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Data structures are preliminarily stored in the buffer in groups based on their identifiers before the actual vector construction is needed. This preliminary organization allows subsequent vector assembly operations to proceed efficiently without requiring additional memory access operations, thereby reducing energy consumption during the critical vector formation phase.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10437594B2Apparatus and method for transferring a plurality of data structures between memory and one or more vectors of data elements stored in a register bank
Publication Date: 2019.10.08 ARM LTD
  • US10437594B2 patent drawing
  • US10437594B2 patent drawing
  • US10437594B2 patent drawing

AI summary

An apparatus and method are provided for transferring a plurality of data structures from memory into one or more vectors of data elements stored in a register bank. The apparatus has first interface circuitry to receive data structures retrieved from memory, where each data structure has an associated identifier and comprises N data elements. Multi-axial buffer circuitry is provided having an array of storage elements, where along a first axis the array is organized as N sets of storage elements, each set containing a plurality VL of storage elements, and where along a second axis the array is organized as groups of N storage elements, with each group containing a storage element from each of the N sets. Access control circuitry then stores the N data elements of a received data structure in one of the groups selected in dependence on the associated identifier. Responsive to an indication that all required data structures have been stored in the multi-axial buffer circuitry, second interface circuitry then outputs the data elements stored in one or more of the sets of storage elements as one or more corresponding vectors of data elements for storage in a register bank, each vector containing VL data elements. Such an approach can significantly increase the performance of handling such load operations, and give rise to potential energy savings.