Multi-Bank Dual-Pipe SRAM Architecture for Frequency Doubling
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Solution Overview
Problem
Single-bank Quad-B2 SRAMs are limited in maximum operating frequency due to the need for sequential execution of read and write operations within a single clock cycle, which restricts performance and cannot be improved by utilizing multiple pipelines.
Innovation Solution
Implementing a multi-bank, dual-pipe SRAM architecture where read and write operations alternate between two sets of pipelines, allowing each operation pair to be executed over two cycles, thereby doubling the maximum operating frequency without increasing pipeline propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If single-bank SRAM executes Read and Write operations sequentially within a single clock cycle, then the operations can be completed together, but the maximum operating frequency is limited to one divided by the minimum execution time
Solution Approach 1:
The SRAM is divided into multiple banks (at least two), allowing Read and Write operations to be directed to different banks simultaneously. This segmentation enables parallel execution of operation pairs across different banks, effectively doubling the maximum operating frequency from 1/tRW to 2/tRW by utilizing multiple independent memory banks that can operate concurrently without interfering with each other.
2Productivity
If multiple pipelines are added to single-bank SRAM, then throughput may increase, but the maximum operating frequency cannot be improved beyond the sequential execution limit
Solution Approach 1:
Instead of adding complexity in the time dimension with multiple pipelines within a single bank, the invention transitions to the bank dimension by creating multiple independent memory banks. This dimensional shift allows parallel operation pairs to execute simultaneously across banks, achieving frequency doubling without the complex inter-pipeline coordination required in single-bank multi-pipeline architectures.
Data Source
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AI summary
Systems and methods are disclosed for increasing the performance of static random access memory (SRAM). Various systems herein, for example, may include or involve dual- or multi-pipe, multi-bank SRAMs, such as Quad-B2 SRAMs. In one illustrative implementation, there is provided an SRAM memory device including a memory array comprising a plurality of SRAM banks and pairs of separate and distinct pipes associated with each of the SRAM banks, wherein each pair of pipes may provide independent access to its associated SRAM bank.