Multi-bank Memory Organization for Bandwidth and Area Trade-off
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Solution Overview
Problem
Conventional multi-port SRAM systems face significant area overhead due to the large size of multi-port SRAM cells, limiting their usage to small memory instances, and existing solutions fail to efficiently multiply available cyclic random bandwidth with minimal area overhead.
Innovation Solution
A memory system with multiple ports and multiple memory banks, each using single-port memory cells, where simultaneous accesses can be performed across all ports at the top level without addressing the same bank, and an additional hierarchy of partitions further multiplies accessible ports with minimal area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-port SRAM cells are used to increase available random bandwidth, then the number of simultaneous accesses is improved, but the area overhead increases enormously
Solution Approach 1:
The memory system is divided into multiple independent memory banks (first memory bank, second memory bank, etc.), each using standard single-port SRAM cells. This segmentation allows simultaneous accesses to different banks through different ports without requiring complex multi-port cells, thus achieving high bandwidth with minimal area overhead.
Solution Approach 2:
Each memory port is designed to be universal, capable of accessing any memory bank through multiplexer structures. The multiplexers allow a single port to dynamically connect to different banks, enabling flexible simultaneous accesses across multiple ports without dedicating specific ports to specific banks, thereby maximizing bandwidth utilization without increasing cell complexity.
2Productivity
If multi-port SRAM cells are used to increase transaction generation frequency, then the number of concurrent accesses is improved, but the cell size increases restricting usage to small memory instances
Solution Approach 1:
The system segments the memory into multiple banks, each using simple single-port SRAM cells rather than complex multi-port cells. This segmentation maintains small cell size while achieving high transaction generation frequency through parallel accesses to different banks via multiple ports with multiplexer control.
3Productivity
If multiple memory banks with multiple ports are implemented to multiply cyclic random bandwidth, then the bandwidth is improved, but the system complexity increases
Solution Approach 1:
Each port is designed as a universal interface that can access any memory bank through multiplexer structures. The multiplexers dynamically route port access requests to the appropriate banks, enabling any port to service any bank. This universal design achieves multiplied cyclic random bandwidth while managing system complexity through standardized, flexible interconnection rather than dedicated point-to-point connections.
Solution Approach 2:
Multiplexer structures serve as intermediaries between ports and memory banks. The multiplexers manage the routing and arbitration of access requests, decoupling the ports from specific banks and simplifying the overall system control logic while enabling flexible simultaneous accesses across multiple banks and ports.
Data Source
AI summary
A memory system includes multiple (N) memory banks and multiple (M) ports, wherein N is greater than or equal to M. Each of the memory banks is coupled to each of the ports. Access requests are transmitted simultaneously on each of the ports. However, each of the simultaneous access requests specifies a different memory bank. Each memory bank monitors the access requests on the ports, and determines whether any of the access requests specify the memory bank. Upon determining that an access request specifies the memory bank, the memory bank performs an access to an array of single-port memory cells. Simultaneous accesses are performed in multiple memory banks, providing a bandwidth equal to the bandwidth of one memory bank times the number of ports. An additional level of hierarchy may be provided, which allows further multiplication of the number of simultaneously accessed ports, with minimal area overhead.