Multi-Bank Memory Concurrent Read-Write Access
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Solution Overview
Problem
Conventional single-port and dual/multi-port memories face challenges in providing simultaneous read and write access while balancing area and leakage penalties, as they either require more transistors or duplicate peripheral circuits, limiting efficient concurrent operations.
Innovation Solution
A multi-bank memory system with first and second local controllers for each memory bank, along with a global controller that sends concurrent read and write instructions to different memory banks, allowing simultaneous operations without the need for additional transistors or duplicated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional two-port or multi-port memories are used to provide simultaneous read and write access, then concurrent access capability is improved, but the area occupied on the chip increases due to more transistors
Solution Approach 1:
The memory system is divided into multiple independent memory banks, each with its own local controller. This segmentation allows different banks to operate independently and concurrently, enabling simultaneous read and write operations without requiring multi-port memory elements, thus reducing the area penalty while maintaining productivity.
2Productivity
If separate memories are used to avoid same-location access conflicts, then simultaneous read and write access is enabled, but area penalty increases due to duplication of peripheral circuits
Solution Approach 1:
Multiple single-port memory banks are merged into a unified memory system under a global controller. This allows the system to achieve simultaneous access capability without duplicating peripheral circuits, as the banks share common control and data paths managed by the global controller, reducing area while maintaining productivity.
Solution Approach 2:
A global controller acts as an intermediary between the processor and multiple memory banks. It receives memory access requests, determines the appropriate bank and operation type, and coordinates access to enable simultaneous read and write operations without requiring each memory unit to have full peripheral circuit duplication.
3Productivity
If dual- or multi-port memories are selected for simultaneous access, then concurrent operations are enabled, but leakage penalties increase
Solution Approach 1:
The memory is segmented into multiple single-port banks that can be independently activated. This allows the system to enable concurrent operations by activating only the necessary banks rather than keeping all ports of a multi-port memory active, thereby reducing leakage power while maintaining productivity.
Data Source
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AI summary
A memory includes at least first and second banks of single-port memory elements, a first local controller adapted to send read and write instructions to the first memory bank, and a second local controller adapted to send read and write instructions to the second memory bank. A global controller is configured to receive first and second memory addresses and a first indication of an operation to be performed at the first memory addresses and a second indication of an operation to be performed at the second memory address and to instruct the first local controller to perform the first indicated operation at the first memory address and to instruct the second local controller to perform the second indicated operation at the second memory address at the same time.