Multi-Bank Memory Controller for Stable Parity Error Correction
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Solution Overview
Problem
Memory systems experience operational performance degradation due to unpredictable errors or failures that are difficult for controllers to manage, leading to non-uniform distribution and inefficiencies.
Innovation Solution
A memory system architecture that pairs banks within memory devices, utilizing a controller to read and process data from multiple banks to generate codewords for error correction, thereby improving operational performance and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a memory device operates with multiple banks, then data reading capability is improved, but error correction difficulty increases due to non-uniform fail distribution
Solution Approach 1:
The memory device is divided into multiple banks (first bank and second bank), each capable of independent data storage and reading operations. This segmentation allows parallel data reading from different banks, improving overall data reading capability while enabling targeted error correction in specific banks when failures occur.
Solution Approach 2:
The controller acts as an intermediary that manages read operations from multiple banks and coordinates error correction processes. It reads data from both the first bank and second bank, processes the combined data, and manages parity information to correct errors, thereby resolving the complexity of error correction in multi-bank systems.
2Reliability
If error correction is performed using parity bits, then error correction capability is improved, but power consumption increases
Solution Approach 1:
The system uses a limited number of parity bits (K bits) to correct errors in the read data. Instead of using excessive error correction mechanisms that would consume more power, the system optimizes the parity bit allocation to achieve effective error correction with minimal energy overhead, correcting only when and where errors occur.
Solution Approach 2:
The error correction mechanism operates autonomously by automatically detecting and correcting errors using parity information without requiring external intervention. The controller self-manages the error correction process, reading data from banks, processing parity information, and correcting errors as needed, thereby reducing the need for additional power-consuming external correction systems.
3Speed
If data is read from multiple banks simultaneously, then reading speed is improved, but system complexity increases
Solution Approach 1:
The controller merges read operations from multiple banks into a unified data processing workflow. By simultaneously reading data from the first bank and second bank and then processing the combined data as a single codeword, the system achieves parallel reading speed benefits while managing complexity through integrated control rather than separate management of each bank.
Solution Approach 2:
The controller performs multiple functions: it reads data from both banks, processes the combined data into codewords, manages error correction, and handles parity information. This multi-functionality in a single controller reduces the need for separate dedicated circuits for each function, thereby managing system complexity while maintaining high reading speeds through parallel bank access.
Data Source
AI summary
When processing data corresponding to a command, a memory system processes the data by operating at least two banks included in a memory device. The operation of the banks according to the command is distributed, so the number of bits of data provided from a bank in which an error occurs is reduced, and the error may be corrected using a parity of a smaller number of bits.