Multi-Bank Memory Device for Simultaneous Multi-Processor Access
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Solution Overview
Problem
Current memory devices struggle to efficiently handle simultaneous memory access requests from multiple processors, leading to decreased system performance due to inadequate bandwidth and increased manufacturing costs, power consumption, and complexity when using multiple memory devices.
Innovation Solution
A memory device with multiple sub-banks and independently driven data channels, allowing for simultaneous processing of memory access requests, where each sub-bank has a distinct address area and includes sense amplifiers, and the number of data channels can be adjusted based on the number of requests, connected through a memory controller for efficient data input/output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If one uses a plurality of memory devices to handle multiple processor accesses, then the memory access capability is improved, but the manufacturing cost, system size, and power consumption increase
Solution Approach 1:
The memory device is divided into multiple memory banks (first memory bank, second memory bank, etc.), each capable of independent operation. This segmentation allows simultaneous processing of multiple memory access requests from different processors without requiring multiple separate memory devices, thereby improving memory access capability while maintaining a single integrated device structure.
Solution Approach 2:
A single memory device is designed to handle multiple processor accesses simultaneously through its multi-bank architecture and multiple data channels. The memory device universally serves multiple processors (first processor, second processor, etc.) through a shared command and control signal port and address port, eliminating the need for dedicated memory devices for each processor.
2Speed
If one increases the operational frequency to increase bandwidth, then the instantaneous maximum bandwidth is improved, but the effective bandwidth does not increase as expected due to sequential processing limitations
Solution Approach 1:
The memory device is divided into multiple memory banks (first memory bank, second memory bank, etc.), each capable of independent operation. This segmentation allows simultaneous processing of multiple memory access requests from different processors without requiring multiple separate memory devices, thereby improving memory access capability while maintaining a single integrated device structure.
Solution Approach 2:
Multiple data channels (first data channel, second data channel, etc.) are provided to enable continuous and simultaneous data transmission for multiple memory access requests. This allows the memory device to maintain continuous useful action by processing multiple requests in parallel rather than sequentially, thereby increasing effective bandwidth.
3Device complexity
If one uses a single memory device for multiple processors, then the manufacturing cost and system size are reduced, but the memory cannot respond to requests in time when processors simultaneously access different address areas
Solution Approach 1:
The memory device is divided into multiple memory banks (first memory bank, second memory bank, etc.), each capable of independent operation. This segmentation allows simultaneous processing of multiple memory access requests from different processors without requiring multiple separate memory devices, thereby improving memory access capability while maintaining a single integrated device structure.
Solution Approach 2:
The memory device dynamically allocates different memory banks and data channels to different processors based on access patterns. The system can adaptively handle simultaneous access requests by directing them to appropriate banks and channels, optimizing response time for dynamic multi-processor workloads while maintaining a compact single-device structure.
Data Source
AI summary
A memory device for multiple processors capable of processing a plurality of memory access requests and a memory system having the same are provided. The memory device includes one command and control signal port configured to receive a command and control signal from a memory controller, one address port configured to receive an address signal from the memory controller, a data port configured to form a plurality of data channels being independently driven to simultaneously process a plurality of memory access requests of the memory controller, and a plurality of memory banks divided into a plurality of sub-banks to simultaneously perform operations according to the plurality of memory access requests when the plurality of memory access requests are sequentially transmitted through the command and control signal port and the address port.