Multi-bank Memory Device Programmable Latency Control
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Solution Overview
Problem
Conventional memory devices require data registers (FIFO) to manage latency, increasing circuit area and manufacturing costs, especially when accessing multiple memory banks sequentially.
Innovation Solution
A multi-bank memory device with a programmable latency time allows data from multiple memory banks to be continuously output to a common data bus, eliminating the need for external data registers (FIFO) by using a control circuit to manage data access and output timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data registers (FIFO) are used to manage access latency in conventional memory devices, then data access continuity is improved, but circuit area and manufacturing costs increase
Solution Approach 1:
The patent removes the external FIFO data registers from the memory system by integrating latency management functionality directly into the control circuit. The control circuit now internally handles the buffering and timing of data from multiple banks without requiring separate external buffer components, thereby reducing circuit area while maintaining continuous data access capability
Solution Approach 2:
The patent combines the latency management function previously performed by external FIFO registers with the control circuit. The control circuit now integrates both the control logic and the data buffering functionality, merging multiple components into a single integrated unit that reduces overall circuit area and component count
2Productivity
If data registers (FIFO) are used to buffer continuous burst data, then data output timing is improved, but manufacturing costs increase
Solution Approach 1:
The patent eliminates the need for external FIFO data registers by extracting their buffering function and integrating it into the control circuit. This integration removes additional components and interconnections, simplifying the overall system and reducing manufacturing complexity and costs while maintaining proper data output timing
Solution Approach 2:
The control circuit is designed to perform multiple functions: it controls address decoding, manages data timing for multiple banks, and provides internal buffering capabilities. This multi-functional design replaces what would otherwise require separate dedicated FIFO components, reducing component count and manufacturing costs while maintaining data output timing requirements
3Adaptability or versatility
If multiple memory banks are accessed sequentially through a common data bus, then data access flexibility is improved, but access latency increases
Solution Approach 1:
The control circuit performs preliminary actions by pre-fetching data from multiple memory banks and buffering it internally before the actual data output is required. This advance preparation allows the system to maintain flexible sequential access to multiple banks while hiding the latency through internal buffering, so that data is ready for immediate output when needed
Solution Approach 2:
The control circuit acts as an intermediary between multiple memory banks and the common data bus. It manages the timing and coordination of data transfer from multiple banks, buffering data internally to mask the sequential access latency. This intermediary function allows flexible access to multiple banks while maintaining the appearance of continuous data flow to the external interface
Data Source
AI summary
A memory device includes a common data bus, a plurality of memory banks and a control circuit. The memory banks are coupled to the common data bus. The memory banks share the common data bus. Each of the memory banks includes a storage device and a data register. The data register is coupled between the storage device the common data bus, and is arranged for storing data read from the storage device. The control circuit is coupled to storage devices and data registers of the memory banks, and is arranged for referring to an address signal and an access signal to control the storage device of said each memory bank to output the data to the corresponding data register, and referring to the address signal and a programmable latency time to control the data registers to output data from the memory banks to the common data bus.