Multi-bank Memory with Parallel Read Write Ports
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Solution Overview
Problem
Existing memory systems face inefficiencies in simultaneous read and write access to memory banks, particularly in handling multiple requests within a single clock cycle, as they often require logical-to-virtual address translation and struggle with managing conflicts between read and write operations.
Innovation Solution
A memory system with multiple single-port memory banks divided into groups, where write commands provide data without specifying storage locations, and the system selects available storage locations without logical-to-virtual address translation, using redundancy information to reconstruct data when necessary, and caching updated redundancy information for efficient execution of multiple read and write commands in a single clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple read and write commands are executed in the same clock cycle using traditional memory systems, then command execution throughput increases, but address translation complexity and memory access conflicts increase
Solution Approach 1:
The memory system is divided into multiple independent memory banks (first memory bank, second memory bank, etc.), each capable of handling read and write commands independently. This segmentation allows parallel command execution across different banks without requiring complex address translation, as each bank operates autonomously with its own command queue and control logic.
Solution Approach 2:
The system pre-allocates command queues for each memory bank and pre-establishes the mapping between command ports and memory banks. When commands arrive, they are routed to appropriate banks based on pre-configured rules rather than requiring dynamic address translation. This preliminary setup enables efficient multi-command execution while avoiding complex translation overhead.
2Productivity
If multiple read commands access the same memory bank simultaneously, then read throughput increases, but read conflicts occur requiring redundancy data access and reconstruction
Solution Approach 1:
Read commands are distributed to different memory banks based on bank indexing, ensuring that simultaneous reads access different physical banks. This segmentation eliminates read conflicts entirely, as each bank handles only one read command per clock cycle. The system achieves high read throughput through parallel access to multiple banks rather than through conflict resolution mechanisms.
Solution Approach 2:
Instead of allowing multiple reads to the same bank and resolving conflicts through redundancy data (as in traditional systems), this invention inverts the approach by distributing reads to different banks from the outset. The conflict prevention strategy replaces the conflict resolution strategy, simplifying the system architecture.
3Manufacturing precision
If write commands specify explicit storage locations, then write precision increases, but write-read conflict management becomes more difficult
Solution Approach 1:
Write commands are routed to specific memory banks based on bank selection logic that considers both the target location and current bank usage status. Each bank independently manages its write operations, and the control logic ensures that writes to the same bank are serialized while allowing parallel writes to different banks. This segmentation approach maintains write precision while simplifying conflict management through distributed control.
Solution Approach 2:
The system performs preliminary bank selection and command scheduling before executing write operations. By pre-determining which bank will handle each write command based on address patterns and current bank availability, the system avoids write-read conflicts without requiring complex real-time arbitration. This preliminary scheduling enables precise write location specification while maintaining simple conflict management.
4Adaptability or versatility
If logical-to-physical address translation is implemented, then address mapping flexibility increases, but access time and system complexity increase
Solution Approach 1:
The patent extracts and eliminates the logical-to-physical address translation stage from the memory access path. Commands use direct physical addresses that map straightforwardly to memory banks, removing the translation overhead. This extraction maintains sufficient flexibility for address mapping while dramatically reducing access time by eliminating an entire processing stage.
Solution Approach 2:
Instead of translating logical addresses to physical addresses (traditional approach), the system inverts the model by using physical addresses directly as command inputs. This inversion eliminates translation time while maintaining address mapping flexibility through direct bank selection based on physical address patterns.
Data Source
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Figure 3
AI summary
A method for data storage includes receiving one or more read commands and one or more write commands, for execution in a same clock cycle in a memory array that comprises multiple single-port memory banks divided into groups. The write commands provide data for storage but do not specify storage locations in which the data is to be stored. One or more of the groups, which are not accessed by the read commands in the same clock cycle, are selected. Available storage locations are chosen for the write commands in the single-port memory banks of the selected one or more groups. During the same clock cycle, the data provided in the write commands is stored in the chosen storage locations, and the data requested by the read commands is retrieved. Execution of the write commands is acknowledged by reporting the chosen storage locations.