Multi-bank Memory with Dynamic Bank Reassignment for Read-Write Collision Resolution
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Solution Overview
Problem
Existing multi-port memory systems face challenges in executing read and write commands simultaneously across single-port memory banks within a single clock cycle, as single-port memory banks can only handle one command per cycle, leading to inefficiencies and collisions when accessing the same bank.
Innovation Solution
The implementation of a memory system with control logic that designates redundant entries across memory banks, allowing read and write commands to be executed in different banks within the same cycle by using a logical-to-physical mapping table to manage addresses and reassign redundant entries dynamically, enabling multiple commands per clock cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-port memory banks are used to reduce device complexity and cost, then manufacturing cost and device size are reduced, but the ability to execute multiple commands simultaneously is limited
Solution Approach 1:
The memory system is divided into multiple single-port memory banks, each capable of independent operation. This segmentation allows the system to achieve multi-command execution by distributing commands across different banks, rather than requiring each bank to support multiple ports.
Solution Approach 2:
Single-port memory banks are made universal by implementing a control logic that can dynamically assign different banks to handle read or write operations. The same bank can serve different functions at different times, and the system as a whole achieves multi-port functionality through coordinated use of multiple single-port banks.
2Speed
If read and write commands are executed in the same memory bank simultaneously, then command execution speed is improved, but command collisions occur causing errors
Solution Approach 1:
A control logic unit acts as an intermediary between command inputs and memory banks. This mediator receives read and write commands, determines their target banks, and coordinates execution to prevent collisions. The control logic ensures that simultaneous operations target different banks or are sequenced appropriately, maintaining reliability while enabling parallel execution.
3Productivity
If multiple write commands are executed in the same clock cycle in different memory banks, then data storage throughput is improved, but address mapping complexity increases
Solution Approach 1:
The system performs preliminary actions by pre-organizing data into stripes that are distributed across multiple memory banks. Write commands operate on entire stripes simultaneously, and the address mapping logic is simplified by using predictable patterns based on stripe assignments rather than requiring complex per-address routing decisions.
Data Source
AI summary
A method for data storage includes, in a network element, receiving from packet-processing circuitry at least a read command and a write command, for execution in a memory array that includes multiple single-port memory banks. When the read command and the write command are to access different memory banks in the memory array, the read command and the write command are executed for the packet-processing circuitry in the different memory banks in a same memory-access cycle. When the read command and the write command are both to access a first memory bank, a second memory bank of the memory array is selected. The read command is executed in the first memory bank and the write command is executed in the second memory bank, in the same memory-access cycle.