Multi-bank Memory Architecture with Non-shared Sense Amplifier Bands
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Solution Overview
Problem
Current DDR3 memory devices face timing issues due to disparate signal path lengths between eight banks, leading to complex control and increased latency, as conventional approaches like placing half banks on each side of the chip double the number of column decoders and move them farther away from I/O pads.
Innovation Solution
A multi-bank block architecture is introduced, where each bank has a non-shared sense amplifier band, and separate data paths are provided, with common Y-Select lines, allowing for flexible spare Y select lines and simplified datapath control, reducing signal path lengths and improving speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If all eight banks share common I/O paths to reach I/O pads, then device complexity is reduced, but signal path lengths become disparate leading to timing issues and increased latency
Solution Approach 1:
The patent divides the eight banks into two separate groups, each with its own dedicated I/O paths and column decoders. This segmentation eliminates the timing issues caused by disparate signal path lengths while maintaining manageable device complexity through organized separation of banks into distinct groups with independent signal paths.
2Loss of time
If half banks are placed on each side of the chip to separate I/O paths, then timing issues are ameliorated, but the number of column decoders doubles and they are placed farther from I/O pads
Solution Approach 1:
The patent segments banks into groups while sharing column decoder resources within each group. This approach achieves timing performance improvement through separate I/O paths while avoiding the penalty of doubling column decoders by implementing shared decoder architecture within segmented groups.
Solution Approach 2:
The patent implements shared column decoders that serve multiple banks within a group, making these decoders multi-functional. This universality reduces the total number of column decoders needed compared to having dedicated decoders for each bank, while still providing separate I/O paths for timing performance.
3Speed
If separate data paths are provided for each bank with non-shared sense amplifier bands, then datapath length is shortened and speed is enhanced, but device complexity increases
Solution Approach 1:
The patent introduces non-shared sense amplifier bands between banks to create separate data paths, which shortens datapath length and enhances speed. The segmentation is organized into groups that manage complexity through structured separation rather than complete isolation of all components.
Data Source
AI summary
A multi-bank block architecture for integrated circuit memory devices which effectively reduces the total length of the datapath for a given input/output (I/O) from the memory cells in the memory array to the actual device I/O pad. In accordance with the present, a memory block in a memory device is effectively divided into two or more banks, and between these banks an additional non-shared sense amplifier band is added as a sense amplifier cannot be shared across a bank boundary. Within this multi-bank block, separate data paths are provided for the banks with the column (Y-Select) lines being common.